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1. 发明授权

US07948023B2 Semiconductor device including nonvolatile memory and method for fabricating the same 有权
标题翻译：包括非易失性存储器的半导体器件及其制造方法
公开(公告)号：US07948023B2
公开(公告)日：2011-05-24
申请号：US12506315
申请日：2009-07-21
申请人： Masataka Takebuchi , Fumitaka Arai
发明人： Masataka Takebuchi , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

2. 发明申请

US20090283815A1 SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包含非易失性存储器的半导体器件及其制造方法
公开(公告)号：US20090283815A1
公开(公告)日：2009-11-19
申请号：US12506315
申请日：2009-07-21
申请人： Masataka Takebuchi , Fumitaka Arai
发明人： Masataka Takebuchi , Fumitaka Arai
IPC分类号： H01L27/112 , H01L29/78
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

3. 发明授权

US07282413B2 Semiconductor device including nonvolatile memory and method for fabricating the same 有权
标题翻译：包括非易失性存储器的半导体器件及其制造方法
公开(公告)号：US07282413B2
公开(公告)日：2007-10-16
申请号：US11318501
申请日：2005-12-28
申请人： Masataka Takebuchi , Fumitaka Arai
发明人： Masataka Takebuchi , Fumitaka Arai
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

4. 发明申请

US20060102950A1 Semiconductor device including nonvolatile memory and method for fabricating the same 有权
公开(公告)号：US20060102950A1
公开(公告)日：2006-05-18
申请号：US11318501
申请日：2005-12-28
申请人： Masataka Takebuchi , Fumitaka Arai
发明人： Masataka Takebuchi , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.

5. 发明授权

US06376879B2 Semiconductor device having MISFETs 有权
标题翻译：具有MISFET的半导体器件
公开(公告)号：US06376879B2
公开(公告)日：2002-04-23
申请号：US09327517
申请日：1999-06-08
申请人： Seiichi Mori , Toshiharu Watanabe , Masataka Takebuchi , Kazuaki Isobe
发明人： Seiichi Mori , Toshiharu Watanabe , Masataka Takebuchi , Kazuaki Isobe
IPC分类号： H01L2978
CPC分类号： H01L21/76897 , H01L21/823425 , H01L27/10873 , H01L27/10894
摘要： A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.
摘要翻译：第一侧壁膜形成在高电压晶体管的栅电极的侧面上，第二侧壁膜设置在第一侧壁膜上。第一侧壁膜的蚀刻速率低于预金属电介质的蚀刻速率，并且第二侧壁膜的蚀刻速率基本上等于前金属电介质的蚀刻速率。高压晶体管的LDD设置在半导体衬底的位于第一和第二侧壁膜正下方的部分中。高压晶体管的源极/漏极扩散层形成在第二侧壁膜外侧的基板的那部分。蚀刻速度低于预金属电介质的蚀刻速率的第一侧壁膜和/或具有与前金属电介质基本上相同的蚀刻速率的第二侧壁膜设置在栅极的侧面低压晶体管的电极。低压晶体管的LDD设置在基板的位于第一侧壁膜正下方的部分。低压晶体管的漏极/源极扩散层设置在分别位于第二侧壁膜的正下方和外侧的基板的两个连续部分中。

6. 发明授权

US5151761A Nonvolatile semiconductor memory device with isolated gate electrodes 失效
标题翻译：具有隔离栅极电极的非挥发性半导体存储器件
公开(公告)号：US5151761A
公开(公告)日：1992-09-29
申请号：US627846
申请日：1990-12-14
申请人： Masataka Takebuchi
发明人： Masataka Takebuchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , H01L27/115
摘要： A nonvolatile semiconductor memory device is disclosed, which includes a semiconductor substrate, a field oxidation film selectively formed on the semiconductor substrate, a first gate insulating film formed on an exposed surface of the semiconductor substrate and on the field oxidation film, a plurality of memory cells, floating gate electrodes and control gate electrodes of the plurality of memory cells, the floating gate and the control gate of each of the memory cells being isolated from those of other adjacent memory cells so as to be formed into an island, an insulating interlayer formed on the field oxidation film and on the control gate electrode, a contact hole extending through the first insulating interlayer so as to expose a portion of the control gate electrode, and a plurality of wires, formed on the insulating interlayer, for connecting the control gate electrodes of memory cells of the plurality of memory cells, which are adjacent to each other in a word line direction, through the first contact hole.

7. 发明申请

US20080029806A1 SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包含非易失性存储器的半导体器件及其制造方法
公开(公告)号：US20080029806A1
公开(公告)日：2008-02-07
申请号：US11865894
申请日：2007-10-02
申请人： Masataka TAKEBUCHI , Fumitaka Arai
发明人： Masataka TAKEBUCHI , Fumitaka Arai
IPC分类号： H01L29/78
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

8. 发明授权

US06900086B2 Semiconductor device having MISFETs 失效
标题翻译：具有MISFET的半导体器件
公开(公告)号：US06900086B2
公开(公告)日：2005-05-31
申请号：US10435380
申请日：2003-05-12
申请人： Seiichi Mori , Toshiharu Watanabe , Masataka Takebuchi , Kazuaki Isobe
发明人： Seiichi Mori , Toshiharu Watanabe , Masataka Takebuchi , Kazuaki Isobe
IPC分类号： H01L21/60 , H01L21/8234 , H01L21/8242 , H01L21/8238
CPC分类号： H01L21/76897 , H01L21/823425 , H01L27/10873 , H01L27/10894
摘要： A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.
摘要翻译：第一侧壁膜形成在高电压晶体管的栅电极的侧面上，第二侧壁膜设置在第一侧壁膜上。第一侧壁膜的蚀刻速率低于预金属电介质的蚀刻速率，并且第二侧壁膜的蚀刻速率基本上等于前金属电介质的蚀刻速率。高压晶体管的LDD设置在半导体衬底的位于第一和第二侧壁膜正下方的部分中。高压晶体管的源极/漏极扩散层形成在第二侧壁膜外侧的基板的那部分。蚀刻速度低于预金属电介质的蚀刻速率的第一侧壁膜和/或具有与前金属电介质基本上相同的蚀刻速率的第二侧壁膜设置在栅极的侧面低压晶体管的电极。低压晶体管的LDD设置在基板的位于第一侧壁膜正下方的部分。低压晶体管的漏极/源极扩散层设置在分别位于第二侧壁膜的正下方和外侧的基板的两个连续部分中。

9. 发明授权

US6018195A MOS gate structure semiconductor device 失效
标题翻译： MOS栅结构半导体器件
公开(公告)号：US6018195A
公开(公告)日：2000-01-25
申请号：US834863
申请日：1997-04-10
申请人： Masataka Takebuchi
发明人： Masataka Takebuchi
IPC分类号： H01L29/41 , H01L21/3205 , H01L21/768 , H01L21/8247 , H01L23/485 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L23/48 , H01L29/40
CPC分类号： H01L23/485 , H01L21/76895 , H01L27/115 , H01L2924/0002
摘要： A high-speed and highly-integrated semiconductor device and a producing method thereof, which can reduce resistance between a gate electrode and a wiring layer on the gate electrode and can make an element minute, are provided. The gate electrodes on a semiconductor substrate, diffusion layers formed in a surface region of the semiconductor substrate, buried electrodes formed on the semiconductor substrate so as to be connected to the diffusion layers respectively, an interlayer insulating film buried in spaces between the gate electrodes and in spaces between the gate electrodes and the buried electrodes, and wiring layers formed so as to be connected to the gate electrodes or to the buried electrodes are provided. A height of surfaces of the gate electrodes, a height of surfaces of the buried electrodes and a height of a surface of the interlayer insulating film are equal, and the surfaces of the gate electrodes, the buried electrodes and the interlayer insulating film form a plane. The wiring layers formed on the plane so as to be directly connected to the surfaces of the gate electrodes and the buried electrodes.
摘要翻译：提供了可以降低栅极电极和栅电极上的布线层之间的电阻并且可以使元件微小的高速且高度集成的半导体器件及其制造方法。半导体衬底上的栅极电极，形成在半导体衬底的表面区域中的扩散层，形成在半导体衬底上的埋入电极分别连接到扩散层，掩埋在栅电极之间的空间中的层间绝缘膜和在栅极电极和埋入电极之间的空间中，设置与栅极电极或埋入电极连接形成的布线层。栅电极的表面的高度，埋入电极的表面的高度和层间绝缘膜的表面的高度相等，并且栅电极，埋电极和层间绝缘膜的表面形成平面。在平面上形成的布线层直接连接到栅电极和埋电极的表面。

10. 发明授权

US5341329A Nonvolatile semiconductor memory device capable of preventing read error caused by overerase state and method therefor 失效
标题翻译：能够防止由过度曝光状态引起的读取误差的非易失性半导体存储器件及其方法
公开(公告)号：US5341329A
公开(公告)日：1994-08-23
申请号：US118285
申请日：1993-09-09
申请人： Masataka Takebuchi
发明人： Masataka Takebuchi
IPC分类号： G11C16/12 , G11C16/26 , G11C16/06
CPC分类号： G11C16/12 , G11C16/26
摘要： A non-volatile semiconductor memory device includes a voltage supply circuit for supplying a positive voltage to the source line or bit line (to which a low biasing voltage is conventionally applied) with respect to each of non-volatile memory cells in a memory cell array in a data read mode. Since this voltage supply circuit applies the positive voltage to the memory cells in the data read mode, an effect equivalent to back gate biasing of the memory cells can be achieved. Accordingly, a memory cell in an overerase state has, a positive threshold voltage in the data read mode.
摘要翻译：一种非易失性半导体存储器件包括用于向存储单元阵列中的每个非易失性存储单元提供正电压到源线或位线（传统施加低偏置电压的位线）的电压供应电路在数据读取模式下。由于该电压供给电路在数据读取模式下向存储单元施加正电压，所以能够实现与存储单元的背栅极偏置相当的效果。因此，过渡状态的存储单元具有数据读取模式中的正阈值电压。

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