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1. 发明申请

US20150348634A1 SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF 审中-公开
标题翻译：半导体存储器件，包括其的存储器系统及其操作方法
公开(公告)号：US20150348634A1
公开(公告)日：2015-12-03
申请号：US14486361
申请日：2014-09-15
申请人： SK hynix Inc.
发明人： Min Gyu KOO , Hyun HEO , Dong Hwan LEE
IPC分类号： G11C16/14 , G11C16/26 , G11C16/24
CPC分类号： G11C16/24 , G11C16/16
摘要： A semiconductor memory device includes a plurality of memory cells coupled between a source line and a bit line, a voltage generation circuit suitable for applying an erase voltage to the source line during an erase operation, and a read and to circuit coupled to the bit line through a selection transistor and suitable for applying an operating voltage to a first node of the selection transistor during the erase operation.
摘要翻译：半导体存储器件包括耦合在源极线和位线之间的多个存储器单元，适用于在擦除操作期间向源极线施加擦除电压的电压产生电路，以及耦合到位线的读取和电路通过选择晶体管并且适于在擦除操作期间将工作电压施加到选择晶体管的第一节点。

2. 发明申请

US20180075915A1 HIGH VOLTAGE SWITCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 审中-公开
公开(公告)号：US20180075915A1
公开(公告)日：2018-03-15
申请号：US15453367
申请日：2017-03-08
申请人： SK hynix Inc.
发明人： Dong Hwan LEE , Min Gyu KOO
IPC分类号： G11C16/30 , H03K17/687
CPC分类号： G11C16/30 , H03K17/102 , H03K17/6872 , H03K17/6877 , H03K2017/6875 , H03K2217/0018 , H03K2217/0054
摘要： Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.

3. 发明申请

US20150064894A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20150064894A1
公开(公告)日：2015-03-05
申请号：US14542197
申请日：2014-11-14
申请人： SK hynix Inc.
发明人： Min Gyu KOO
IPC分类号： H01L27/115
CPC分类号： H01L27/11524 , H01L21/02365 , H01L21/28273 , H01L27/11539 , H01L27/1157 , H01L29/788 , H01L29/7881
摘要： The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.
摘要翻译：半导体器件包括具有由第一隔离层限定的第一有源区的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在所述栅绝缘层上的第一导电层; 形成在所述第一导电层上的电介质层; 至少一个穿过介电层的第一接触孔; 形成在所述电介质层上的第二导电层，所述第二导电层填充所述至少一个第一接触孔以接触所述第一导电层; 以及至少一个第一接触插塞，其连接到所述第一有源区域中的所述第二导电层，其中所述至少一个第一接触插塞从所述至少一个第一接触孔偏移以与所述介电层重叠。

4. 发明申请

US20170323897A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170323897A1
公开(公告)日：2017-11-09
申请号：US15662010
申请日：2017-07-27
申请人： SK hynix Inc.
发明人： Dong Hwan LEE , Min Gyu KOO , Hyun HEO
IPC分类号： H01L27/11529 , H01L29/06 , H01L29/78 , H01L27/11573 , H01L29/66 , H01L27/11526 , H01L27/11582 , H01L27/11556 , H01L27/1157 , H01L21/265 , H01L29/10
摘要： A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.

5. 发明申请

US20160322370A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160322370A1
公开(公告)日：2016-11-03
申请号：US14864159
申请日：2015-09-24
申请人： SK hynix Inc.
发明人： Dong Hwan LEE , Min Gyu KOO , Hyun HEO
IPC分类号： H01L27/115
CPC分类号： H01L27/11529 , H01L21/26586 , H01L27/11526 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/0623 , H01L29/0653 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.
摘要翻译：半导体器件包括具有存储器阵列区域和外围区域的衬底，形成在周边区域中以限定有源区域的隔离层，在有源区域中形成的彼此分离的偏移绝缘层和具有重叠的边缘的栅极电极具有偏移绝缘层并且布置在偏移绝缘层之间的有源区域中。

6. 发明申请

US20150279471A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150279471A1
公开(公告)日：2015-10-01
申请号：US14490484
申请日：2014-09-18
申请人： SK hynix Inc.
发明人： Yeonghun LEE , Hyun HEO , Min Gyu KOO , Dong Hwan LEE
IPC分类号： G11C16/14 , G11C16/28 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/28
摘要： A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.
摘要翻译：半导体器件包括多个存储器块，其中多个存储器块中的每一个包括电耦合到公共源极线的第一选择晶体管，电耦合到位线的第二选择晶体管和电耦合的多个存储器单元第一和第二选择晶体管之间的操作电压，以及适用于对从多个存储块中选择的所选择的存储块施加用于编程操作，读取操作和擦除操作的操作电压的操作电路，并且将第一正电压施加到在擦除操作期间当向公共源极线施加擦除电压时，多个存储器块的未选择存储块中的第一选择晶体管的栅极。

7. 发明申请

US20150288283A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20150288283A1
公开(公告)日：2015-10-08
申请号：US14477593
申请日：2014-09-04
申请人： SK hynix Inc.
发明人： Yeonghun LEE , Hyun HEO , Min Gyu KOO , Dong Hwan LEE
IPC分类号： H02M3/158 , G11C16/10 , G11C16/30
CPC分类号： H02M3/158 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.
摘要翻译：半导体装置包括适于输出高电压的电压供给电路，耦合在电压供给电路和外围电路之间并适于将高电压传送到外围电路的转移电路，以及适于输出转移控制的转移控制电路信号传送到传送电路以控制高电压传送到外围电路，其中传输控制电路在电压供应电路输出具有第一正电压电平的传输控制信号到包括在传送电路中的晶体管的栅极将高电压输出到传输电路。

8. 发明申请

US20140054668A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140054668A1
公开(公告)日：2014-02-27
申请号：US13718808
申请日：2012-12-18
申请人： SK HYNIX INC.
发明人： Min Gyu KOO
IPC分类号： H01L29/788 , H01L21/02
CPC分类号： H01L27/11524 , H01L21/02365 , H01L21/28273 , H01L27/11539 , H01L27/1157 , H01L29/788 , H01L29/7881
摘要： The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.
摘要翻译：半导体器件包括具有由第一隔离层限定的第一有源区的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在所述栅绝缘层上的第一导电层; 形成在所述第一导电层上的电介质层; 至少一个穿过介电层的第一接触孔; 形成在所述电介质层上的第二导电层，所述第二导电层填充所述至少一个第一接触孔以接触所述第一导电层; 以及至少一个第一接触插塞，其连接到所述第一有源区域中的所述第二导电层，其中所述至少一个第一接触插塞从所述至少一个第一接触孔偏移以与所述介电层重叠。

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