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1. 发明申请

US20080085609A1 METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS 审中-公开
标题翻译：保护低地层地区高原地区的方法
公开(公告)号：US20080085609A1
公开(公告)日：2008-04-10
申请号：US11461033
申请日：2006-07-31
申请人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
发明人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L27/105 , H01L27/11526 , H01L27/11539
摘要： A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on at least a portion of only the at least one high-topography region, wherein the high-topography region comprises a plurality of semiconductor devices of a first type. The method further comprises patterning a thin photo-resist layer having a second thickness, wherein the first thickness is greater than the second thickness, such that the patterned thin photo-resist layer is formed on at least a portion of only the at least one low-topography region. The method further comprises forming a plurality of semiconductor devices of a second type in the at least the portion of the low-topography region. The method further comprises removing both the thick photo-resist layer and the thin photo-resist layer.
摘要翻译：提供了一种用于保护具有至少一个高地形区域和至少一个低地形区域的基底上的至少一个高地形区域的方法。该方法包括图案化具有第一厚度的厚的光致抗蚀剂层，使得厚的光致抗蚀剂层形成在仅至少一个高地形区域的至少一部分上，其中高地形区域包括多个的第一类半导体器件。该方法还包括对具有第二厚度的薄的光致抗蚀剂层进行图案化，其中第一厚度大于第二厚度，使得图案化的光致抗蚀剂层形成在至少一个低至少一个的至少一部分上地形区域。该方法还包括在低地形区域的至少一部分中形成第二类型的多个半导体器件。该方法还包括去除厚的光致抗蚀剂层和薄的光致抗蚀剂层。

2. 发明授权

US07670760B2 Treatment for reduction of line edge roughness 失效
标题翻译：减少线边缘粗糙度的处理
公开(公告)号：US07670760B2
公开(公告)日：2010-03-02
申请号：US11369513
申请日：2006-03-06
申请人： Jinmiao James Shen , Jonathan L. Cobb , William D. Darlington , Brian J. Fisher , Mark D. Hall , Vikas R. Sheth , Mehul D. Shroff , James E. Vasek
发明人： Jinmiao James Shen , Jonathan L. Cobb , William D. Darlington , Brian J. Fisher , Mark D. Hall , Vikas R. Sheth , Mehul D. Shroff , James E. Vasek
IPC分类号： G03F1/00
CPC分类号： G03F7/168
摘要： A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
摘要翻译：提供了一种降低光致抗蚀剂层中的线边缘粗糙度（LER）的方法。根据该方法，将一层光致抗蚀剂施加到基底上。然后在包括选自氢，氮和含氟材料的至少一种气体的气氛中对光致抗蚀剂层进行构图和退火。优选地，在图案化光致抗蚀剂之后进行退火，但是在修剪之后或之后。

3. 发明授权

US07276406B2 Transistor structure with dual trench for optimized stress effect and method therefor 有权
标题翻译：具有双沟槽的晶体管结构，用于优化应力效应及其方法
公开(公告)号：US07276406B2
公开(公告)日：2007-10-02
申请号：US10977266
申请日：2004-10-29
申请人： Jian Chen , Michael D. Turner , James E. Vasek
发明人： Jian Chen , Michael D. Turner , James E. Vasek
IPC分类号： H01L21/8238
CPC分类号： H01L21/76283 , H01L21/0274 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7842
摘要： A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a or semiconductor-on-insulator substrate.
摘要翻译：用于形成半导体器件结构的一部分的方法包括提供具有半导体有源层，绝缘层和半导体衬底的绝缘体上半导体衬底。第一隔离沟槽形成在半导体有源层内，并且应力源材料沉积在第一沟槽的底部上，其中应力源材料包括双重用途的膜。第二隔离沟槽形成在半导体有源层内，其中第二隔离沟槽不存在第二沟槽底部上的应力源材料。在第一和第二隔离沟槽中分别存在和不存在应力材料提供差分应力：（i）在半导体器件结构的一个或多个N型或P型器件中，（ii）对于一个或多个的宽度方向或沟道方向取向，以及（iii）定制绝缘体上半导体衬底中的一个或多个的应力益处。

4. 发明授权

US07157377B2 Method of making a semiconductor device using treated photoresist 有权
标题翻译：使用经处理的光致抗蚀剂制造半导体器件的方法
公开(公告)号：US07157377B2
公开(公告)日：2007-01-02
申请号：US10779007
申请日：2004-02-13
申请人： Cesar M. Garza , William D. Darlington , Stanley M. Filipiak , James E. Vasek
发明人： Cesar M. Garza , William D. Darlington , Stanley M. Filipiak , James E. Vasek
IPC分类号： H01L21/311
CPC分类号： H01L21/0273 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L29/66477 , H01L29/78 , Y10S438/945 , Y10S438/947
摘要： A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.
摘要翻译：通过图案化用于形成晶体管的栅极的导电层来制造半导体器件。用于形成栅极的工艺具有将导电层覆盖的光刻胶图形化的步骤。修整图案化的光致抗蚀剂，使其宽度减小。氟，优选F 2 N被施加到修剪的光致抗蚀剂以增加其硬度和对导电层的选择性。使用修剪和氟化光致抗蚀剂作为掩模，蚀刻导电层以形成用作栅极的导电特征。形成导电柱是栅极的晶体管。其他卤素，特别是氯可以代替氟。

5. 发明授权

US07288447B2 Semiconductor device having trench isolation for differential stress and method therefor 有权
标题翻译：具有用于差分应力的沟槽隔离的半导体器件及其方法
公开(公告)号：US07288447B2
公开(公告)日：2007-10-30
申请号：US10977226
申请日：2005-01-18
申请人： Jian Chen , Thien T. Nguyen , Michael D. Turner , James E. Vasek
发明人： Jian Chen , Thien T. Nguyen , Michael D. Turner , James E. Vasek
IPC分类号： H01L21/64
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L29/045 , H01L29/6659 , H01L29/7846
摘要： A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.
摘要翻译：半导体器件具有用于定义有源区的沟槽。在沟槽中沉积薄的扩散屏障之后，选择性地蚀刻一些沟槽以在沟槽中留下不同的区域。其中一个区域具有完全去除扩散阻挡层，使底层被暴露。另一个区域仍然存在扩散屏障。遵循氧化步骤，使得氧化发生在去除扩散阻挡层的拐角处，而氧化被作为氧阻挡的扩散阻挡层阻挡。用于氧化的角是那些需要压应力的角，例如沿着P沟道晶体管的边界的一部分。留下扩散阻挡层的角部是不期望压缩应力的角，例如N沟道晶体管的边界。

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