专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06809034B2 Method of etching metallic thin film on thin film resistor 失效
公开(公告)号：US06809034B2
公开(公告)日：2004-10-26
申请号：US10131683
申请日：2002-04-24
申请人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
发明人： Ichiro Ito , Satoshi Shiraki , Tomio Yamamoto , Makoto Ohkawa , Atsumi Takahashi , Yasuaki Tsuzuki , Akito Fukui , Toshio Sakakibara , Takayuki Sugisaka
IPC分类号： H01L21302
CPC分类号： H01L28/24 , H01L21/32139
摘要： An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

12. 发明申请

US20060071217A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060071217A1
公开(公告)日：2006-04-06
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L31/0312
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

13. 发明授权

US06336245B1 Door stopper 失效
标题翻译：门顶
公开(公告)号：US06336245B1
公开(公告)日：2002-01-08
申请号：US09563850
申请日：2000-05-04
申请人： Toshio Sakakibara
发明人： Toshio Sakakibara
IPC分类号： E05F500
CPC分类号： E05C17/48 , E05F5/02 , E05F5/08 , E05Y2201/212 , E05Y2201/22 , E05Y2201/224 , E05Y2201/232 , E05Y2201/264 , E05Y2201/474 , E05Y2800/11 , Y10T16/61 , Y10T16/625
摘要： The door stopper of the present invention is of a construction such that a door contacting member fitted into a guide cylinder sunk vertically into the floor is allowed to be set in two positions, in a door contacting state in which it protrudes from the floor and in a housed state in which the top is substantially level with the floor. According to this construction, the floor is able to be substantially flat when the door stopper is not in use so that it does not become an obstruction to floor polishers and wheelchairs.
摘要翻译：本发明的门止动器具有这样的结构，使得嵌合在垂直于地板的引导筒中的门接触构件被允许设置在从地板突出的门接触状态的两个位置，并且在一个容纳状态，其中顶部基本上与地面平齐。根据这种结构，当门挡块不使用时，地板能够基本上平坦，使得它不会成为地板抛光机和轮椅的障碍物。

14. 发明授权

US5644157A High withstand voltage type semiconductor device having an isolation region 失效
标题翻译：具有隔离区域的高耐压型半导体器件
公开(公告)号：US5644157A
公开(公告)日：1997-07-01
申请号：US653924
申请日：1996-05-22
申请人： Makio Iida , Shoji Miura , Takayuki Sugisaka , Toshio Sakakibara , Osamu Ishihara
发明人： Makio Iida , Shoji Miura , Takayuki Sugisaka , Toshio Sakakibara , Osamu Ishihara
IPC分类号： H01L21/762 , H01L29/73 , H01L29/732 , H01L27/06 , H01L29/80
CPC分类号： H01L29/7317 , H01L21/76264 , H01L29/7322 , H01L21/76275 , H01L21/76286
摘要： A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.
摘要翻译：能兼容地实现耐压提高和集成度的半导体装置。掩埋集电极区域3和集电极耐压区域4之间的PN结经受反向偏压，并且PN结中的耗尽层到达介电隔离区域9a，该介电隔离区域9a介电地隔离集电极耐压区域4的侧面。与其间的侧绝缘隔离区域9a相邻的集电极耐电压的周向半导体区域14具有接近于基极区域5处的电位，而不是埋藏集电极区域3的电位。结果，耗尽层受到基极区域5和周围半导体区域14两者的低电位的影响。这减轻了基部区域5的侧面与其底部之间的角部附近的静电聚焦，约束雪崩击穿，并提高耐压。

15. 发明授权

US5449946A Semiconductor device provided with isolation region 失效
标题翻译：具有隔离区域的半导体器件
公开(公告)号：US5449946A
公开(公告)日：1995-09-12
申请号：US208119
申请日：1994-03-09
申请人： Toshio Sakakibara , Makio Iida , Takayuki Sugisaka , Shoji Miura
发明人： Toshio Sakakibara , Makio Iida , Takayuki Sugisaka , Shoji Miura
IPC分类号： H01L21/74 , H01L21/762 , H01L21/763 , H01L21/822 , H01L27/04 , H01L29/06 , H01L27/02
CPC分类号： H01L21/76264 , H01L21/743 , H01L21/763 , H01L21/76275 , H01L21/76286
摘要： A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.
摘要翻译：提供了一种半导体器件，其中在导电材料上非常简单地形成接触，以防止电容耦合。两个硅衬底通过氧化硅膜结合。并且在硅基板之一中形成延伸到氧化硅膜的沟槽，以便在多个电路元件之间彼此隔离，并且通过沟槽隔室形成用于电路元件形成的岛。在用于电路元件形成的岛的外周部分上形成氧化硅膜。此外，用于电容耦合防止的岛由用于电路元件形成的岛之间的硅衬底形成，并且被施加到其上以保持恒定的电位。

16. 发明授权

US5017505A Method of making a nonvolatile semiconductor memory apparatus with a floating gate 失效
标题翻译：制造具有浮动栅极的非易失性半导体存储装置的方法
公开(公告)号：US5017505A
公开(公告)日：1991-05-21
申请号：US313898
申请日：1989-02-23
申请人： Tetsuo Fujii , Toshio Sakakibara , Nobuyoshi Sakakibara
发明人： Tetsuo Fujii , Toshio Sakakibara , Nobuyoshi Sakakibara
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , Y10S438/964
摘要： A first polysilicon film serving as an erase gate is deposited on the major surface of a semiconductor substrate on which a field oxide film is formed, so that the surface of the first polysilicon film is roughened. The surface of the first polysilicon film is thermally oxidized to form a first thermal oxide film thereon. During the oxidation, the roughened surface of the first polysilicon film is flattened, and is duplicated by the surface of the first thermal oxide film. A second polysilicon film is deposited on the roughened surface of the first thermal oxide film. The back surface of the second polysilicon film is roughened by the roughened surface of the first thermal oxide film. In this case, the surface of the second polysilicon film is also roughened. The roughened surface of the second polysilicon film is thermally oxidized in the same manner as described above to flatten its surface and to form a second thermal oxide film, the surface of which is roughened. A third polysilicon film serving as a write gate is formed on the second thermal oxide film.
摘要翻译：用作擦除栅极的第一多晶硅膜沉积在其上形成有场氧化膜的半导体衬底的主表面上，使得第一多晶硅膜的表面被粗糙化。第一多晶硅膜的表面被热氧化以在其上形成第一热氧化膜。在氧化期间，第一多晶硅膜的粗糙化表面变平，并被第一热氧化膜的表面复制。在第一热氧化膜的粗糙化表面上沉积第二多晶硅膜。第二多晶硅膜的背面被第一热氧化膜的粗糙化表面粗糙化。在这种情况下，第二多晶硅膜的表面也被粗糙化。第二多晶硅膜的粗糙化表面以与上述相同的方式被热氧化以使其表面变平，并形成第二热氧化膜，其表面被粗糙化。在第二热氧化膜上形成用作写入栅极的第三多晶硅膜。

17. 发明授权

US4774556A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US4774556A
公开(公告)日：1988-09-27
申请号：US887625
申请日：1986-07-21
申请人： Tetsuo Fujii , Nobuyoshi Sakakibara , Toshio Sakakibara , Hiroshi Iwasaki
发明人： Tetsuo Fujii , Nobuyoshi Sakakibara , Toshio Sakakibara , Hiroshi Iwasaki
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/78 , H01L29/86
CPC分类号： H01L27/11568 , H01L21/28273 , H01L27/11556 , H01L29/66825 , H01L29/7881 , H01L29/7883 , H01L27/115 , H01L29/4236
摘要： A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operation regions and extended vertically with a certain gap from the electron maintaining portions, and a control gate disposed within the insulating partition wall on every electron holding portions on the opposite side to the operation region extended vertically and with a certain gap to the electron holding portions, and an impurity region of a second conduction type formed at the surface of the operation region for constituting the other of the drain region or the source region.
摘要翻译：非易失性半导体存储器件包括：第一导电类型的半导体衬底，形成在半导体衬底的表面的第二导电类型的杂质掩埋层，用于构成漏极区域或源极区域中的任一个，外延层形成在所述杂质掩埋层的表面上的第二导电类型的绝缘分隔壁，包围在所述杂质掩埋层中的围绕所述杂质掩埋层的操作区域的外延层的表面垂直延伸的绝缘隔壁，用于限定其中的操作区域，至少一个电子保持部分延伸垂直于操作区域预定的距离并且设置在与操作区域隔离的绝缘分隔壁内，通过具有隧道效应的厚度的绝缘膜的杂质掩埋层或漏极区域，设置在绝缘体内的控制栅极分隔壁设置在侧面上的每个电子保持部分上 e与操作区域相对并且与电子维持部分具有一定间隙垂直延伸;以及控制栅极，设置在绝缘分隔壁内的每个电子保持部分上，与操作区域相对的一侧垂直延伸并且具有一定间隙电子保持部分和形成在用于构成漏极区域或源极区域中的另一个的操作区域的表面处的第二导电类型的杂质区域。

18. 发明授权

US07763893B2 Silicon carbide semiconductor device 失效
标题翻译：碳化硅半导体器件
公开(公告)号：US07763893B2
公开(公告)日：2010-07-27
申请号：US11979753
申请日：2007-11-08
申请人： Eiichi Okuno , Toshio Sakakibara
发明人： Eiichi Okuno , Toshio Sakakibara
IPC分类号： H01L31/0312
CPC分类号： H01L27/088 , H01L21/823487 , H01L29/66068
摘要： A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.
摘要翻译：碳化硅半导体器件包括设置在具有第一导电型碳化硅层和硅衬底的半导体衬底中的半导体元件。该器件包括：在碳化硅层上的沟槽以到达硅衬底; 以及在碳化硅层和硅衬底之间的沟槽中的导电层以连接到它们两者。半导体元件是垂直型半导体元件，使得电流在半导体衬底的顶表面部分和后表面部分两者上流动。电流流过导电层。

19. 发明申请

US20080128711A1 Silicon carbide semiconductor device 失效
标题翻译：碳化硅半导体器件
公开(公告)号：US20080128711A1
公开(公告)日：2008-06-05
申请号：US11979753
申请日：2007-11-08
申请人： Eiichi Okuno , Toshio Sakakibara
发明人： Eiichi Okuno , Toshio Sakakibara
IPC分类号： H01L29/24
CPC分类号： H01L27/088 , H01L21/823487 , H01L29/66068
摘要： A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.
摘要翻译：碳化硅半导体器件包括设置在具有第一导电型碳化硅层和硅衬底的半导体衬底中的半导体元件。该器件包括：在碳化硅层上的沟槽以到达硅衬底; 以及在碳化硅层和硅衬底之间的沟槽中的导电层以连接到它们两者。半导体元件是垂直型半导体元件，使得电流在半导体衬底的顶表面部分和后表面部分两者上流动。电流流过导电层。

20. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式