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1. 发明申请

US20060071217A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060071217A1
公开(公告)日：2006-04-06
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L31/0312
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

2. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

3. 发明授权

US07663181B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07663181B2
公开(公告)日：2010-02-16
申请号：US11206271
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L29/72
CPC分类号： H01L21/823487 , H01L29/7722
摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.
摘要翻译：半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域。半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到来自半导体基底的第二表面的栅极上升金属膜。

4. 发明申请

US20060076613A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060076613A1
公开(公告)日：2006-04-13
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
IPC分类号： H01L29/94
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

5. 发明授权

US07355207B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07355207B2
公开(公告)日：2008-04-08
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

6. 发明授权

US07763504B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US07763504B2
公开(公告)日：2010-07-27
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/338
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

7. 发明申请

US20050258454A1 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20050258454A1
公开(公告)日：2005-11-24
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/04 , H01L21/336 , H01L27/098 , H01L27/10 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

8. 发明申请

US20080153216A1 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US20080153216A1
公开(公告)日：2008-06-26
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/82
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

9. 发明申请

US20070241338A1 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US20070241338A1
公开(公告)日：2007-10-18
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

10. 发明授权

US07855384B2 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US07855384B2
公开(公告)日：2010-12-21
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L29/04 , H01L29/94
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

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