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11. 发明申请

US20060128088A1 Vertical integrated component, component arrangement and method for production of a vertical integrated component 失效
标题翻译：垂直集成部件，组件布置和垂直集成部件生产方法
公开(公告)号：US20060128088A1
公开(公告)日：2006-06-15
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Luyken , Wolfgang Rosner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

12. 发明授权

US07709827B2 Vertically integrated field-effect transistor having a nanostructure therein 失效
标题翻译：其中具有纳米结构的垂直集成的场效应晶体管
公开(公告)号：US07709827B2
公开(公告)日：2010-05-04
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

13. 发明授权

US07411822B2 Nonvolatile memory cell arrangement 有权
标题翻译：非易失性存储单元布置
公开(公告)号：US07411822B2
公开(公告)日：2008-08-12
申请号：US11283572
申请日：2005-11-18
申请人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
发明人： Michael Specht , Franz Hofmann , Ulrich Dorda , Johannes Kretz , Lars Dreeskornfeld
IPC分类号： G11C11/34 , G11C5/06 , H01L27/10 , H01L29/76 , H01L29/40
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.
摘要翻译：存储晶体管被布置成多个行和列。第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接到第二金属化平面中的导电导体轨道。

14. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

15. 发明申请

US20070264595A1 Method for Multiple Irradiation of a Resist 有权
标题翻译：多次照射抗原的方法
公开(公告)号：US20070264595A1
公开(公告)日：2007-11-15
申请号：US11746909
申请日：2007-05-10
申请人： Kang-Hoon Choi , Klaus Elian , Christoph Hohle , Johannes Kretz , Frank Thrum
发明人： Kang-Hoon Choi , Klaus Elian , Christoph Hohle , Johannes Kretz , Frank Thrum
IPC分类号： G03F7/20
CPC分类号： G03F7/203 , G03F7/2022 , G03F7/70466
摘要： The invention relates to a method with contrast reversal which, inter alia, opens up new areas of application for resists.
摘要翻译：本发明涉及一种具有对比度反转的方法，其特别是开辟新的抗蚀剂应用领域。

16. 发明申请

US20070018218A1 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell 审中-公开
标题翻译：鳍场效应晶体管存储单元，鳍场效应晶体管存储单元的布置及制造鳍场效应晶体管存储单元的方法
公开(公告)号：US20070018218A1
公开(公告)日：2007-01-25
申请号：US11455907
申请日：2006-06-19
申请人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
发明人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
IPC分类号： H01L29/94
CPC分类号： H01L29/7923 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833 , H01L29/785
摘要： The invention relates to a bridge field-effect transistor storage cell comprising first and second source/drain areas and a channel area arranged therebetween, which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer that is disposed at least partially on the semiconductor bridge and a metal conductive gate area on at least one part of the charge-coupled layer that is arranged in such a way that electric charge carriers are selectively introducible or removable by applying a predetermined electric voltage to the bridge field-effect transistor storage cell.
摘要翻译：本发明涉及一种桥式场效应晶体管存储单元，其包括形成在半导体桥中的第一和第二源极/漏极区域和布置在其间的沟道区域。本发明的存储单元还包括至少部分地设置在半导体电桥上的电荷耦合层和电荷耦合层的至少一部分上的金属导电栅极区域，其中电荷载体为通过向桥式场效应晶体管存储单元施加预定的电压来选择性地引入或去除。

17. 发明申请

US20060001058A1 Fin field effect transistor memory cell 审中-公开
标题翻译： Fin场效应晶体管存储单元
公开(公告)号：US20060001058A1
公开(公告)日：2006-01-05
申请号：US11157496
申请日：2005-06-20
申请人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
发明人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/42384 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.
摘要翻译：具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层，至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

18. 发明授权

US06528807B1 Method for applying or removing material 有权
标题翻译：施加或去除材料的方法
公开(公告)号：US06528807B1
公开(公告)日：2003-03-04
申请号：US09485210
申请日：2000-02-04
申请人： Hans Wilfried Peter Koops , Johannes Kretz , Hubert Brueckl
发明人： Hans Wilfried Peter Koops , Johannes Kretz , Hubert Brueckl
IPC分类号： H01J37305
CPC分类号： B82B3/00 , G01Q30/12 , G01Q70/06 , G01Q80/00 , G11B9/14 , G11B9/1409 , G11B9/1418 , G11B9/1463 , Y10S977/855 , Y10S977/86 , Y10S977/869 , Y10S977/888
摘要： A process which allows effective application or removal of materials to and from substrates using a scanning probe microscope operated at atmospheric pressure. The substrate is placed in a trough, located on the x-y table of a scanning probe microscope (SXM), and this trough is filled with a liquid and/or gaseous medium up to a level such that the top side of the substrate is covered with a thin layer, composed of at least one monolayer of the medium. For depositing a structured precipitate from the medium or for structuring etching of the surface of the substrate, the microtip of the SXM is then dipped into the layer and supplied with an electric voltage or with voltage pulses. The process can be used for applying or removing materials to and from substrates. The process is also usable for characterization of the geometry and for restoration or the production of microtips of SXM cantilevers, as well as for storing information, for reading information and for erasing information.
摘要翻译：使用在大气压下操作的扫描探针显微镜，可以有效地施加或去除衬底的工艺。将衬底置于位于扫描探针显微镜（SXM）的xy台上的槽中，该槽是填充有液体和/或气体介质，直到基底的顶侧覆盖有由介质的至少一个单层组成的薄层。为了从介质沉积结构沉淀物或用于构造基板表面的蚀刻，然后将SXM的微尖端浸入该层中并提供电压或电压脉冲。该方法可用于施加或去除材料往返于基材。该过程还可用于表征SXM悬臂的几何形状和微型尖头的恢复或生产，以及用于存储信息，用于读取信息和擦除信息。

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