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1. 发明授权

US07807563B2 Method for manufacturing a layer arrangement and layer arrangement 有权
标题翻译：制造层布置和层布置的方法
公开(公告)号：US07807563B2
公开(公告)日：2010-10-05
申请号：US11786770
申请日：2007-04-12
申请人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
发明人： Zvonimir Gabric , Werner Pamler , Guenther Schindler , Gernot Steinlesberger , Andreas Stich , Martin Traving , Eugen Unger
IPC分类号： H01L23/58
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.
摘要翻译：在制造层布置的方法中，多个导电结构嵌入基板中。至少在相邻的导电结构之间去除衬底的材料。在每个导电结构的侧壁的至少一部分上形成中间层。第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。

2. 发明申请

US20090213830A1 COMMUNICATION SYSTEM 失效
标题翻译：具有纳米结构的电路和用于生产纳米结构的接触连接的方法
公开(公告)号：US20090213830A1
公开(公告)日：2009-08-27
申请号：US11577070
申请日：2005-10-11
申请人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
发明人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
IPC分类号： H04J3/00 , H04B1/38 , G08B13/14
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0021
摘要： A communication system is disclosed. In one embodiment, the communication system includes a communication device set up to execute a process, configured to put itself into an activated state or into a deactivated state at alternate times, receive time information in a first operating state of the activated state, take the received time information as a basis for ascertaining the later time at which useful information is transmitted to the communication device, receive the useful information at the later time in a second operating state of the activated state. Individual components of the communication device are able to be put into an activated state or into a deactivated state independently of one another.
摘要翻译：公开了一种电路。该电路包括由基本上碳层形成的至少一个纳米结构和碳互连，其中纳米结构和碳互连彼此直接耦合。

3. 发明申请

US20070018218A1 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell 审中-公开
标题翻译：鳍场效应晶体管存储单元，鳍场效应晶体管存储单元的布置及制造鳍场效应晶体管存储单元的方法
公开(公告)号：US20070018218A1
公开(公告)日：2007-01-25
申请号：US11455907
申请日：2006-06-19
申请人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
发明人： Johannes Kretz , Franz Kreupl , Michael Specht , Gernot Steinlesberger
IPC分类号： H01L29/94
CPC分类号： H01L29/7923 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833 , H01L29/785
摘要： The invention relates to a bridge field-effect transistor storage cell comprising first and second source/drain areas and a channel area arranged therebetween, which are formed in a semiconductor bridge. The inventive storage cell also comprises a charge-coupled layer that is disposed at least partially on the semiconductor bridge and a metal conductive gate area on at least one part of the charge-coupled layer that is arranged in such a way that electric charge carriers are selectively introducible or removable by applying a predetermined electric voltage to the bridge field-effect transistor storage cell.
摘要翻译：本发明涉及一种桥式场效应晶体管存储单元，其包括形成在半导体桥中的第一和第二源极/漏极区域和布置在其间的沟道区域。本发明的存储单元还包括至少部分地设置在半导体电桥上的电荷耦合层和电荷耦合层的至少一部分上的金属导电栅极区域，其中电荷载体为通过向桥式场效应晶体管存储单元施加预定的电压来选择性地引入或去除。

4. 发明授权

US06946386B2 Process for producing ultrathin homogenous metal layers 有权
标题翻译：生产超薄均质金属层的方法
公开(公告)号：US06946386B2
公开(公告)日：2005-09-20
申请号：US10854759
申请日：2004-05-25
申请人： Gernot Steinlesberger , Manfred Engelhardt , Eugen Unger
发明人： Gernot Steinlesberger , Manfred Engelhardt , Eugen Unger
IPC分类号： C23C18/31 , C23C28/02 , H01L21/4763
CPC分类号： C23C18/31 , C23C28/023
摘要： A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.
摘要翻译：形成用于形成集成电子部件的接触位置和/或接触焊盘和/或布线的基底金属化的超薄均匀金属层的方法。该方法包括以下步骤：至少在区域中在衬底上沉积第一金属层，并且至少在区域中在第一金属层上产生第二金属层，第二金属层的组分具有更正的氧化还原电位其中第二金属层的超薄均匀沉积通过湿化学，无电流的电化学氧化还原过程通过元素交换从一种或多种金属盐作为氧化剂与至少一个顶部进行第一金属层的金属原子层作为还原剂。

5. 发明申请

US20050118342A1 Process for depositing a catalyst 审中-公开
标题翻译：沉积催化剂的方法
公开(公告)号：US20050118342A1
公开(公告)日：2005-06-02
申请号：US10980011
申请日：2004-11-03
申请人： Manfred Engelhardt , Gernot Steinlesberger , Eugen Unger
发明人： Manfred Engelhardt , Gernot Steinlesberger , Eugen Unger
IPC分类号： B01J23/745 , B01J23/755 , B01J37/03 , C01B31/02 , C23C18/16 , C23C18/31 , B05D3/02
CPC分类号： B82Y30/00 , B01J23/745 , B01J23/755 , B01J37/03 , B82Y40/00 , C01B32/162 , C23C18/161 , C23C18/54
摘要： A process for the selective and areal deposition of a catalyst is disclosed, which is intended for the growth of nanotubes, on an interconnect line in an integrated circuit or chip. The process includes providing an acidic or alkaline aqueous solution of the catalyst; applying the solution to the interconnect line; and removing the excess solution.
摘要翻译：公开了用于在集成电路或芯片的互连线上用于纳米管生长的选择性和面积沉积催化剂的方法。该方法包括提供催化剂的酸性或碱性水溶液; 将解决方案应用于互连线; 并除去多余的溶液。

6. 发明申请

US20090046499A1 INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ 审中-公开
标题翻译：集成电路，包括有限读数的存储器
公开(公告)号：US20090046499A1
公开(公告)日：2009-02-19
申请号：US12026249
申请日：2008-02-05
申请人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
发明人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0059 , G11C13/0061 , G11C13/0097 , G11C16/3431 , G11C16/349 , G11C2013/0047 , G11C2013/0052 , G11C2013/0092
摘要： An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.
摘要翻译：一种集成电路，包括具有存储器单元阵列的存储器，每个存储器单元包括非易失性存储元件; 以及通信地耦合到存储器单元阵列的有限读取电路。

7. 发明申请

US20080126624A1 Memory buffer and method for buffering data 审中-公开
标题翻译：内存缓冲区和缓冲数据的方法
公开(公告)号：US20080126624A1
公开(公告)日：2008-05-29
申请号：US11604665
申请日：2006-11-27
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Gernot Steinlesberger , Maurizio Skerlj , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Gernot Steinlesberger , Maurizio Skerlj , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F3/00
CPC分类号： G11C7/1051 , G06F13/1673 , G11C5/04 , G11C7/1006 , G11C7/106
摘要： A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.
摘要翻译：存储器缓冲器包括可连接到存储器控制器和存储器缓冲器中的至少一个的第一异步锁存链接口，连接到存储器件的第二数据接口以及包括缓冲器和处理器的电路，该电路耦合到第一和第二接口，使得数据可以在第一接口和缓冲器之间以及第二接口和缓冲器之间传递，使得处理器能够处理从第一接口到第二接口的数据中的至少一个以及根据数据处理功能的来自第二接口的数据，其中处理器的数据处理功能可以通过经由存储器缓冲器的接口接收的编程信号来改变。

8. 发明授权

US08664657B2 Electrical circuit with a nanostructure and method for producing a contact connection of a nanostructure 失效
标题翻译：具有纳米结构的电路和用于产生纳米结构的接触连接的方法
公开(公告)号：US08664657B2
公开(公告)日：2014-03-04
申请号：US11577070
申请日：2005-10-11
申请人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
发明人： Georg Duesberg , Franz Kreupl , Robert Seidel , Gernot Steinlesberger
IPC分类号： H01L29/00 , H01L29/04 , H01L29/10
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0021
摘要： A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
摘要翻译：公开了一种电路。电路包括由基本上碳层形成的至少一个纳米结构和碳互连，其中纳米结构和碳互连彼此直接耦合。

9. 发明申请

US20090268513A1 MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY 审中-公开
标题翻译：具有不同类型相位变化记忆的存储器件
公开(公告)号：US20090268513A1
公开(公告)日：2009-10-29
申请号：US12111774
申请日：2008-04-29
申请人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
发明人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
IPC分类号： G11C11/00 , G11C7/00 , H01L21/00
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2211/5641 , G11C2213/71 , G11C2213/79
摘要： A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.
摘要翻译：存储器包括包括相变存储器单元的阵列的第一存储器件。第一存储器件是第一存储器类型。集成电路包括包括相变存储器单元的阵列的第二存储器件。第二存储器件是与第一存储器类型不同的第二存储器类型。第一和第二存储器件一起封装成单个存储器件。

10. 发明申请

US20090199043A1 ERROR CORRECTION IN AN INTEGRATED CIRCUIT WITH AN ARRAY OF MEMORY CELLS 审中-公开
标题翻译：在具有存储单元阵列的集成电路中的错误校正
公开(公告)号：US20090199043A1
公开(公告)日：2009-08-06
申请号：US12023523
申请日：2008-01-31
申请人： Peter Schrogmeier , Jan Boris Philipp , Thomas Happ , Luca DeAmbroggi , Christian Pho Duc , Franz Kreupl , Gernot Steinlesberger
发明人： Peter Schrogmeier , Jan Boris Philipp , Thomas Happ , Luca DeAmbroggi , Christian Pho Duc , Franz Kreupl , Gernot Steinlesberger
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C29/44 , G11C29/70 , G11C29/76 , G11C29/81 , G11C2029/0411 , G11C2229/723
摘要： An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.
摘要翻译：集成电路包括存储器单元的阵列，以及错误校正码电路，其被配置为至少部分地基于识别阵列中不规则存储器单元的位置的映射来校正从阵列读取的数据中的错误。

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