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1. 发明申请

US20060001058A1 Fin field effect transistor memory cell 审中-公开
标题翻译： Fin场效应晶体管存储单元
公开(公告)号：US20060001058A1
公开(公告)日：2006-01-05
申请号：US11157496
申请日：2005-06-20
申请人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
发明人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/42384 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.
摘要翻译：具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层，至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

2. 发明申请

US20090086523A1 Integrated circuit and method of forming an integrated circuit 审中-公开
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20090086523A1
公开(公告)日：2009-04-02
申请号：US11904783
申请日：2007-09-28
申请人： Jessica Hartwich , Lars Dreeskornfeld
发明人： Jessica Hartwich , Lars Dreeskornfeld
IPC分类号： G11C5/06 , H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/10897 , H01L29/785
摘要： An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of a portion of the gate electrode is disposed at the same height as an upper side of a portion of the bitline. A method of manufacturing an integrated circuit comprises the steps of forming a memory cell array and forming a support circuitry. The step of forming the memory cell array comprises forming a bitline and forming a wordline disposed above the bitline. The step of forming the support circuitry comprises forming a FinFET. The step of forming the FinFET comprises forming a gate electrode, an upper side of a portion of the gate electrode being formed at the same height as an upper side of a portion of the bitline.
摘要翻译：集成电路包括存储单元阵列部分和支持电路部分。存储单元阵列部分包括设置在位线上方的至少一个位线和至少一个字线。支撑电路部分包括包括栅电极的FinFET。栅电极的一部分的上侧设置在与位线的一部分的上侧相同的高度。一种制造集成电路的方法包括以下步骤：形成存储单元阵列并形成支持电路。形成存储单元阵列的步骤包括形成位线并形成设置在位线上方的字线。形成支撑电路的步骤包括形成FinFET。形成FinFET的步骤包括形成栅电极，栅电极的一部分的上侧形成在与位线的一部分的上侧相同高度处。

3. 发明申请

US20100078711A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER 有权
标题翻译：制造集成电路的方法，其中包括具有栅极间隔的FET
公开(公告)号：US20100078711A1
公开(公告)日：2010-04-01
申请号：US12242039
申请日：2008-09-30
申请人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
发明人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译：一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。薄片凹进。翅片由薄片的中心部分形成。翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

4. 发明申请

US20090057778A1 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT 失效
标题翻译：集成电路及制造集成电路的方法
公开(公告)号：US20090057778A1
公开(公告)日：2009-03-05
申请号：US11848857
申请日：2007-08-31
申请人： Lars Dreeskornfeld , Jessica Hartwich , Tobias Mono , Arnd Scholz , Stefan Slesazeck
发明人： Lars Dreeskornfeld , Jessica Hartwich , Tobias Mono , Arnd Scholz , Stefan Slesazeck
IPC分类号： H01L27/085 , H01L21/8239
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译：包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管，第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。

5. 发明申请

US20080197384A1 Field Effect Transistor Arrangement 审中-公开
标题翻译：场效应晶体管布置
公开(公告)号：US20080197384A1
公开(公告)日：2008-08-21
申请号：US12035195
申请日：2008-02-21
申请人： Jessica Hartwich , Lars Dreeskornfeld , Gernot Steinlesberger
发明人： Jessica Hartwich , Lars Dreeskornfeld , Gernot Steinlesberger
IPC分类号： H01L29/423 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/41783 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon.
摘要翻译：场效应晶体管布置包括电绝缘层，源极区，漏极区和布置在源极区和漏极区之间的沟道区，其中源区，漏区和沟道区分别布置在或超过电绝缘层，以及具有电绝缘栅极层和导电栅极层的栅极区域，其邻接沟道区域或者与沟道区域相距一定距离并且至少部分地沿沟道区域延伸，其中，源极区域和漏极区域在每种情况下由导电碳生成，并且其中沟道区域由应变硅产生。

6. 发明授权

US07863136B2 Method of manufacturing integrated circuits including a FET with a gate spacer and a fin 有权
标题翻译：制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET
公开(公告)号：US07863136B2
公开(公告)日：2011-01-04
申请号：US12242039
申请日：2008-09-30
申请人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
发明人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译：一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。薄片凹进。翅片由薄片的中心部分形成。翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

7. 发明授权

US07622354B2 Integrated circuit and method of manufacturing an integrated circuit 失效
标题翻译：集成电路和集成电路制造方法
公开(公告)号：US07622354B2
公开(公告)日：2009-11-24
申请号：US11848857
申请日：2007-08-31
申请人： Lars Dreeskornfeld , Jessica Hartwich , Tobias Mono , Arnd Scholz , Stefan Slesazeck
发明人： Lars Dreeskornfeld , Jessica Hartwich , Tobias Mono , Arnd Scholz , Stefan Slesazeck
IPC分类号： H01L21/339
CPC分类号： H01L27/10876 , H01L21/84 , H01L21/86 , H01L27/10879 , H01L29/785
摘要： An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.
摘要翻译：包括存储器件的集成电路包括阵列部分，其包括存储器单元和导电线，导电线的上表面设置在半导体衬底的表面下方，以及支撑部分，包括第一类型的晶体管，第一类型包括第一栅电极，该第一栅电极包括垂直于第一类型的晶体管的沟道垂直相邻的垂直部分。

8. 发明申请

US20080283910A1 INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20080283910A1
公开(公告)日：2008-11-20
申请号：US11748864
申请日：2007-05-15
申请人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
发明人： Lars Dreeskornfeld , Dongping Wu , Jessica Hartwich , Juergen Holz , Arnd Scholz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823456 , H01L21/823431 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.
摘要翻译：公开了一种形成集成电路的集成电路和方法。一个实施例包括具有第一栅极和第二类型的具有第二栅电极的FinFET的第一类型的FinFET。第一栅电极形成在限定在半导体衬底中的栅极沟槽中，并且第二栅电极的一部分的底侧设置在半导体衬底的主表面上方。

9. 发明授权

US07189988B2 Molecular electronics arrangement and method for producing a molecular electronics arrangement 有权
标题翻译：分子电子学布置和分子电子学布置方法
公开(公告)号：US07189988B2
公开(公告)日：2007-03-13
申请号：US10482719
申请日：2002-07-01
申请人： Jessica Hartwich , Johannes Kretz , Richard Johannes Luyken , Wolfgang Rösner
发明人： Jessica Hartwich , Johannes Kretz , Richard Johannes Luyken , Wolfgang Rösner
IPC分类号： H01L35/24
CPC分类号： G11C13/0019 , B82Y10/00 , G11C13/0014 , H01L51/0048 , H01L51/005 , H01L51/0052 , H01L51/0093 , H01L51/0595
摘要： The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.
摘要翻译：本发明涉及一种分子电子装置，其包括基底，至少一个具有表面并且布置在基底中或基底上的第一条状导体，隔离物，其被布置在至少一个第一条状导体的表面上，并且部分覆盖所述至少一个第一带状导体的表面和布置在所述间隔件上并包括以平面方式面对所述至少一个第一带状导体的表面的表面的至少一个第二条状导体。所述间隔件部分地覆盖所述至少一个第二条状导体的表面，并且限定所述至少一个第一条状导体和所述至少一个第二条状导体之间的预定距离。本发明的分子电子学装置还包括分子电子学分子，其分布在至少一个第一带状导体的表面的自由区域和至少一个第二条状导体的表面的自由区域之间，所述分子的长度为基本上等于所述至少一个第一带状导体和所述至少一个第二带状导体之间的距离。本发明还涉及生产分子电子装置的方法。

10. 发明申请

US20080299722A1 Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure 审中-公开
标题翻译：用于形成凹陷沟道晶体管的制造方法，用于形成相应的集成半导体存储器件的方法和相应的自对准掩模结构
公开(公告)号：US20080299722A1
公开(公告)日：2008-12-04
申请号：US11807550
申请日：2007-05-29
申请人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
发明人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876 , H01L29/4236 , H01L29/945
摘要： The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.
摘要翻译：本发明提供了一种用于形成凹陷沟道晶体管的方法，包括以下步骤：在具有上表面的半导体衬底中形成多个有源区线，所述线被具有不同于衬底表面的上表面高度的分割结构分割 ; 形成布置在所述有效区域上方并邻近所述分割结构的第一和第二延伸区域; 在所述延伸区域之间的有源区段的剩余部分中的有源区段中形成凹陷通道器件。

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