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11. 发明授权

US06958291B2 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US06958291B2
公开(公告)日：2005-10-25
申请号：US10654757
申请日：2003-09-04
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

12. 发明授权

US06706577B1 Formation of dual gate oxide by two-step wet oxidation 失效
标题翻译：通过两步湿氧化形成双栅氧化物
公开(公告)号：US06706577B1
公开(公告)日：2004-03-16
申请号：US09298879
申请日：1999-04-26
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L27/10894
摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.
摘要翻译：描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将形成。半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。低电压有源区域用掩模覆盖。半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。去除面具。一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极集成电路。

13. 发明授权

US06239023B1 Method to reduce the damages of copper lines 有权
公开(公告)号：US06239023B1
公开(公告)日：2001-05-29
申请号：US09320757
申请日：1999-05-27
申请人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76838 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

14. 发明授权

US6165052A Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation 有权
标题翻译：具有浅沟槽隔离的半导体衬底的化学/机械平面化（CMP）的方法和装置
公开(公告)号：US6165052A
公开(公告)日：2000-12-26
申请号：US192518
申请日：1998-11-16
申请人： Chen-Hua Yu , Syun-Ming Jang
发明人： Chen-Hua Yu , Syun-Ming Jang
IPC分类号： B24B37/04 , B24B49/16 , H01L21/306 , B24B1/00
CPC分类号： B24B37/013 , B24B37/04 , B24B37/042 , B24B49/16 , H01L21/30625
摘要： A method to planarize the surface of a semiconductor substrate having shallow trench isolation (STI) reduces erosion of a silicon nitride planarization stop layer, reduces dishing of large areas of the shallow trench isolation, and prevents under polishing of the surface of the semiconductor substrate that will leave portions of the silicon dioxide that fills the shallow trenches covering the silicon nitride planarization stop exposed, is described. The method to planarize the surface of a semiconductor substrate having shallow trenches begins by chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize the semiconductor substrate. Polishing at a first product of platen pressure and platen speed will cause a high rate of material removal with low selectivity to increase production throughput. The silicon nitride stop layer will be examined to determine an end point exposure of the silicon nitride stop layer. When the end point exposure of the silicon nitride stop layer is reached, chemical/mechanical planarization polishing at a low product of platen pressure and platen speed is started to planarize the semiconductor substrate of slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion. The method further has the step of buffing the surface of the semiconductor substrate to remove any residue from the chemical/mechanical planarization polishing and to remove any microscratches from the surface of the semiconductor substrate.
摘要翻译：平坦化具有浅沟槽隔离（STI）的半导体衬底的表面的方法减少了氮化硅平坦化停止层的侵蚀，减少了大面积浅沟槽隔离的凹陷，并且防止在半导体衬底的表面的抛光将描述填充覆盖氮化硅平坦化止挡露出的浅沟槽的二氧化硅部分。平面化具有浅沟槽的半导体衬底的表面的方法开始于在压板压力和压板速度的第一乘积上的化学/机械平面化抛光，以使半导体衬底平坦化。在压板压力和压板速度的第一个产品上进行抛光将导致高选择性的材料去除率，从而提高生产量。将检查氮化硅阻挡层以确定氮化硅阻挡层的端点暴露。当达到氮化硅终止层的终点曝光时，开始以压板压力和压板速度的低乘积进行化学/机械平面化抛光，以平缓化缓慢过抛光的半导体衬底，以控制浅层的沟槽氧化物的厚度沟槽隔离以减少凹陷和最小化侵蚀。该方法还具有抛光半导体衬底的表面以从化学/机械平面化抛光中除去任何残余物并从半导体衬底的表面去除任何微细凹凸的步骤。

15. 发明授权

US6114253A Via patterning for poly(arylene ether) used as an inter-metal dielectric 有权
标题翻译：通过用作金属间电介质的聚（亚芳基醚）图案化
公开(公告)号：US6114253A
公开(公告)日：2000-09-05
申请号：US268542
申请日：1999-03-15
申请人： Syun-Ming Jang , Ming-Hsin Huang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ming-Hsin Huang , Chen-Hua Yu
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/31055
摘要： A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.
摘要翻译：描述了用于去除用于蚀刻低k有机聚合物介电层中的通孔的残余氧化硅硬掩模的工艺。当用于在高密度等离子体蚀刻机中在氧气/惰性气体等离子体中蚀刻有机聚合物层时，通过沿着图案边缘开发角度方面或刻面，硬掩模劣化。此外，在有机聚合物蚀刻期间硬掩模的劣化导致表面平面度的显着降低，这会在将硬掩模留在原位时在其上形成第二金属层时导致通孔到通孔短路。在通过等离子体蚀刻的通孔蚀刻之后立即选择性地去除残余硬掩模，该等离子体蚀刻恢复表面平面度并且经由边缘面移除。等离子体蚀刻具有高的氧化物对有机聚合物的选择性，使得表面不规则性不会转移到聚合物表面，并且通孔底部的暴露的金属表面也是无损的。

16. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

17. 发明授权

US5871886A Sandwiched middle antireflection coating (SMARC) process 失效
标题翻译：三明治中抗反射涂层（SMARC）工艺
公开(公告)号：US5871886A
公开(公告)日：1999-02-16
申请号：US764288
申请日：1996-12-12
申请人： Chen-Hua Yu , Syun-Ming Jang
发明人： Chen-Hua Yu , Syun-Ming Jang
IPC分类号： G03F7/09 , H01L21/027 , G03F7/00
CPC分类号： H01L21/0276 , G03F7/091
摘要： A method of patterning a layer of reflective material, such as a layer of conductor metal, using a layer of antireflection coating material sandwiched between two layers of photoresist. A first layer of photoresist is formed on an integrated circuit wafer and provides a planar surface for subsequent layers of material. A layer of antireflection coating material is formed on the layer of first photoresist and a layer of second photoresist is formed on the layer of antireflection coating material. The layer of second photoresist is selectively exposed and developed. The layer of antireflection coating material is patterned using dry etching and the patterned layer of second photoresist as a mask. The layer of first photoresist is then patterned using dry etching and the patterned layer of antireflection coating material as a mask. The layer of reflecting material is then patterned using dry etching and the patterned layer of first photoresist as a mask. The patterned layer of first photoresist is then removed.
摘要翻译：使用夹在两层光致抗蚀剂之间的抗反射涂层层来图案化反射材料层（例如导体金属层）的方法。在集成电路晶片上形成第一层光致抗蚀剂，并为随后的材料层提供平面。在第一光致抗蚀剂层上形成防反射涂层，在抗反射涂层层上形成第二光致抗蚀剂层。选择性地曝光和显影第二光致抗蚀剂层。使用干蚀刻和第二光致抗蚀剂的图案化层作为掩模来图案化抗反射涂层材料层。然后使用干蚀刻和防反射涂层材料的图案化层作为掩模来将第一光致抗蚀剂层图案化。然后使用干蚀刻和第一光致抗蚀剂的图案化层作为掩模来图案化反射材料层。然后去除第一光致抗蚀剂的图案化层。

18. 发明授权

US5747380A Robust end-point detection for contact and via etching 失效
标题翻译：用于接触和通孔蚀刻的鲁棒端点检测
公开(公告)号：US5747380A
公开(公告)日：1998-05-05
申请号：US606833
申请日：1996-02-26
申请人： Chen-Hua Yu , Syun-Ming Jang
发明人： Chen-Hua Yu , Syun-Ming Jang
IPC分类号： H01L21/66 , H01L21/768 , H01L21/44
CPC分类号： B24B37/013 , H01L21/768 , H01L22/26 , Y10S438/926
摘要： A method for improving the end-point detection for contact and via etching is disclosed. The disclosure describes the deliberate addition of dummy patterns in the form of contact and via holes to the regular functional holes in order to increase the amount of etchable surface area. It is shown that, one can then take advantage of the marked change in the composition of the etchant gas species that occurs as soon as what was once a large exposed area has now been consumed through the etching process. This then gives a strong and robust signal for the end of the etching process. This in turn results in better controlled and more reliable product. It is also indicated that with the full uniform pattern of the via layers now possible, the chemical/mechanical polishing process becomes much less pattern sensitive.
摘要翻译：公开了一种用于改善接触和通孔蚀刻的端点检测的方法。本公开描述了将接触孔和通孔形式的虚拟图案有意添加到常规功能孔，以增加可蚀刻表面积的量。可以看出，一旦现在通过蚀刻工艺消耗了大的暴露区域，就可以利用所发生的蚀刻剂气体种类的组成的明显变化。这就为腐蚀过程的结束提供了一个强大而鲁棒的信号。这反过来导致更好的控制和更可靠的产品。还指出，现在可能通孔层的完全均匀图案，化学/机械抛光工艺变得更加模式敏感。

19. 发明授权

US5731241A Self-aligned sacrificial oxide for shallow trench isolation 失效
标题翻译：用于浅沟槽隔离的自对准牺牲氧化物
公开(公告)号：US5731241A
公开(公告)日：1998-03-24
申请号：US857160
申请日：1997-05-15
申请人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.
摘要翻译：本发明提供了一种在沟槽氧化物40上制造牺牲自对准亚大气压化学气相沉积（SACVD）O3 TEOS层5070的方法，以保护沟槽氧化物免于过多的后续蚀刻步骤。 SACVD O3 TEOS层在沟槽氧化物层40上的沉积速率高于周围的非沟槽热生长焊盘氧化物。沟槽氧化物优选使用PECVD，LPTEOS或O3-TEOS的工艺形成。本发明提供了两个优选实施例：（1）在氧化层蚀刻之前沉积的第一自对准牺牲O 3 TEOS氧化物层50和（2）在牺牲注入氧化物蚀刻之前沉积的第二自对准牺牲O 3 TEOS氧化物层70。本发明可以应用于各种情况，其中沟槽氧化物暴露于有害蚀刻。

20. 发明授权

US5702977A Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer 失效
标题翻译：采用自对准和平面化沟槽填充介质层的浅沟槽隔离方法
公开(公告)号：US5702977A
公开(公告)日：1997-12-30
申请号：US810390
申请日：1997-03-03
申请人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer. The trench fill layer is formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.
摘要翻译：一种在集成电路内的衬底内的沟槽内形成平坦化沟槽填充层的方法。首先提供其中形成有沟槽的衬底。在沟槽内的不同于沟槽内的区域的基底上形成第一集成电路层，该第一集成电路层具有阻止在沟槽填充层的第一集成电路层上形成的组成，后者形成在衬底上并在沟槽内。在沟槽内还形成在衬底上的不在沟槽内的衬底上的第二集成电路层，该第二集成电路层具有促进在沟槽填充层的沟槽内形成的组成，其随后形成在衬底上并在衬底内沟。最后，在衬底上并在沟槽内形成沟槽填充层。沟槽填充层形成为在沟槽上方的厚度，使得当沟槽填充层通过化学机械抛光（CMP）平面化方法平坦化时，避免在形成在沟槽内的平坦化沟槽填充层内形成皿。

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