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1. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

2. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

3. 发明授权

US6020249A Method for photo alignment after CMP planarization 失效
公开(公告)号：US6020249A
公开(公告)日：2000-02-01
申请号：US891088
申请日：1997-07-10
申请人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
发明人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： G03F9/00 , H01L23/544 , H01L23/48
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002
摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

4. 发明授权

US5923996A Method to protect alignment mark in CMP process 失效
标题翻译：在CMP工艺中保护对准标记的方法
公开(公告)号：US5923996A
公开(公告)日：1999-07-13
申请号：US867312
申请日：1997-06-02
申请人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
发明人： Tsu Shih , Jui-Yu Chang , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/46 , H01L21/301 , H01L21/78
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54493 , H01L2924/0002
摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.
摘要翻译：公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。通过蚀刻将对准标记凹入衬底来提供完整的保护。在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。因此，对准标记设置有保护凹槽而没有额外的步骤。此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

5. 发明授权

US6043133A Method of photo alignment for shallow trench isolation chemical-mechanical polishing 失效
标题翻译：浅沟槽隔离化学机械抛光的光对准方法
公开(公告)号：US6043133A
公开(公告)日：2000-03-28
申请号：US121708
申请日：1998-07-24
申请人： Syun-Ming Jang , Ying-Ho Chen , Jui-Yu Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jui-Yu Chang , Chen-Hua Yu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate. In a key step, the reverse tone trench isolation resist layer 42B is used to etch the first dielectric layer 38 from over the alignment marks 30 and the Active areas 27. Next, the remaining first dielectric layer 38 is chemical-mechanical polished thereby planarizing the first dielectric layer 38.
摘要翻译：本发明提供从超过对准标记30去除浅沟槽隔离（STI）氧化物层38的方法。本发明具有两个主要特征：（1）STI光刻胶掩模42A，用于蚀刻对准区域沟槽34周围的对准标记30并蚀刻设备区域14中的STI沟槽35; 和（2）用于从对准标记30上方和从有源区域37上方去除隔离氧化物38的“反向色调”STI光刻胶掩模42B。该方法开始于提供具有器件区域14的衬底10，对准标记沟槽区域16; 和对准标记区域18.在衬底10上形成抛光阻挡层20 22.沟槽隔离抗蚀剂层42A用于蚀刻围绕器件区域中的对准标记34和STI沟槽35的对准区域沟槽34。介电层38形成在衬底上。在关键步骤中，反向色调沟槽隔离抗蚀剂层42B用于从对准标记30和有源区27上方蚀刻第一介电层38.接下来，剩余的第一介电层38进行化学机械抛光，从而平面化第一电介质层38。

6. 发明授权

US06559040B1 Process for polishing the top surface of a polysilicon gate 有权
标题翻译：抛光多晶硅栅极顶表面的工艺
公开(公告)号：US06559040B1
公开(公告)日：2003-05-06
申请号：US09421517
申请日：1999-10-20
申请人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
发明人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , H01L21/28035
摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.
摘要翻译：抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

7. 发明授权

US06242356B1 Etchback method for forming microelectronic layer with enhanced surface smoothness 有权
标题翻译：用于形成具有增强的表面光滑度的微电子层的Etchback方法
公开(公告)号：US06242356B1
公开(公告)日：2001-06-05
申请号：US09465230
申请日：1999-12-17
申请人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
发明人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L21311
CPC分类号： H01L21/28123 , H01L21/28035 , H01L21/28525 , H01L21/32115
摘要： A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.
摘要翻译：在微电子制造中形成微电子层的方法首先采用衬底。然后在衬底上形成目标微电子层。然后在目标微电子层上形成牺牲平滑层。最后，从目标微电子层完全蚀刻牺牲平滑层，同时与目标微电子层相比，部分蚀刻目标微电子层以形成具有增强的表面光滑度的部分蚀刻的目标微电子层。

8. 发明授权

US06049137A Readable alignment mark structure formed using enhanced chemical mechanical polishing 失效
标题翻译：使用增强的化学机械抛光形成可读取的对准标记结构
公开(公告)号：US06049137A
公开(公告)日：2000-04-11
申请号：US106331
申请日：1998-06-29
申请人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.
摘要翻译：可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。提供了包括产品区域12和对准标记区域30的半导体衬底10。对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

9. 发明授权

US5786260A Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing 失效
标题翻译：使用增强的化学机械抛光制造可读取的对准标记结构的方法
公开(公告)号：US5786260A
公开(公告)日：1998-07-28
申请号：US767015
申请日：1996-12-16
申请人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.
摘要翻译：可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。提供了包括产品区域12和对准标记区域30的半导体衬底10。对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

10. 发明授权

US5773360A Reduction of surface contamination in post-CMP cleaning 失效
标题翻译：减少后CMP清洁中的表面污染
公开(公告)号：US5773360A
公开(公告)日：1998-06-30
申请号：US734067
申请日：1996-10-18
申请人： Chung-Long Chang , Chen-Hua Yu , Syun-Ming Jang
发明人： Chung-Long Chang , Chen-Hua Yu , Syun-Ming Jang
IPC分类号： H01L21/3105 , H01L21/461
CPC分类号： H01L21/31053 , Y10S438/906 , Y10S438/959
摘要： Chemical-mechanical polishing is followed with a scrubbing procedure for the removal of any particulate contaminants. Scrubbing is succeeded by a plasma etching step, using a parallel electrode plasma etcher, a downstream plasma etcher, or similar apparatus. Plasma etching is performed for about 30 seconds using CF.sub.4 as the etching gas, so that about 300 Angstroms of the post CMP surface is removed. This results in the almost total elimination of residual mobile ions from the polished surface without the introduction of microgrooves and similar blemishes as is often the case when HF is used for this purpose.
摘要翻译：随后进行化学机械抛光，用于除去任何颗粒污染物的洗涤程序。通过等离子体蚀刻步骤，使用平行电极等离子体蚀刻器，下游等离子体蚀刻器或类似装置来完成擦洗。使用CF 4作为蚀刻气体进行等离子体蚀刻约30秒，从而去除后CMP表面的约300埃。这导致几乎完全消除了抛光表面的残余移动离子，而不会引入微槽和类似的瑕疵，如通常用于此目的的HF的情况。

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