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11. 发明授权

US07930662B1 Methods for automatically generating fault mitigation strategies for electronic system designs 有权
标题翻译：自动生成电子系统设计故障缓解策略的方法
公开(公告)号：US07930662B1
公开(公告)日：2011-04-19
申请号：US12264283
申请日：2008-11-04
申请人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
发明人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.
摘要翻译：公开了用于产生电子系统设计的方法。在一种方法中，对于设计的第一规范的一个或多个组件中的每一个，响应于与设计的第一规范相关联的用户指定的数据，从多个不同的误差减轻技术中选择错误减轻技术。从第一规格自动生成设计的第二个规范。第二规范包括与针对所述一个或多个组件中的每个组件的每个所选择的误差减轻技术相对应的误差减轻逻辑设计的第二个规格被存储用于后续处理。

12. 发明授权

US07249010B1 Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA 有权
标题翻译：估计在FPGA中实现的设计对单事件不匹配的敏感性的方法
公开(公告)号：US07249010B1
公开(公告)日：2007-07-24
申请号：US10407280
申请日：2003-04-03
申请人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
发明人： Prasanna Sundararajan , Carl H. Carmichael , Scott P. McMillan , Brandon J. Blodget , Cameron D. Patterson
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F13/00 , G06F17/50 , G06F9/00 , G01R31/08 , G01F19/00 , G06F11/34 , G06F15/00 , G21C17/00 , H03K17/693 , H03K17/687
CPC分类号： G06F17/5054 , G06F2217/70
摘要： Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.
摘要翻译：估计在FPGA中实现的设计对单事件扰乱（SEU）的敏感性的方法。在FPGA中，许多配置存储单元可以响应于SEU而改变状态，而不影响在FPGA中实现的设计的功能。根据本发明的方法，确定“关心位”（与设计中实际使用的资源相关联的位）的数量。保留位的数量占FPGA中配置存储单元总数的比例决定了“SEU概率影响”（SEUPI）值。 “平均平均故障间隔时间”（MTBU）值是在FPGA中的一个配置存储器单元受SEU影响之前平均估计经过多少时间。为了获得FPGA中设计的“平均故障间隔时间”，MTBU值除以SEUPI值。

13. 发明授权

US07227378B2 Reconfiguration of a programmable logic device using internal control 有权
标题翻译：使用内部控制重新配置可编程逻辑器件
公开(公告)号：US07227378B2
公开(公告)日：2007-06-05
申请号：US11100971
申请日：2005-04-07
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
摘要翻译：一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

14. 发明授权

US08473904B1 Generation of cache architecture from a high-level language description 有权
标题翻译：从高级语言描述生成缓存架构
公开(公告)号：US08473904B1
公开(公告)日：2013-06-25
申请号：US12009272
申请日：2008-01-16
申请人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
发明人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
IPC分类号： G06F9/44 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/44 , G06F8/433 , G06F12/00 , G06F13/00 , G06F13/28 , G06F17/5054
摘要： Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.
摘要翻译：描述从高级语言描述生成缓存体系结构。获得了以高级编程语言的应用程序的描述。从适于在硬件中提供实现的描述生成数据流表示。生成包括：识别与描述相关联的存储器的访问; 确定对存储器的至少一部分访问不具有用于本地可缓存数据的一个或多个数据依赖性; 并将该部分分配给分布式高速缓存。

15. 发明授权

US07852107B1 Single event upset mitigation 有权
标题翻译：单次事件不安缓解
公开(公告)号：US07852107B1
公开(公告)日：2010-12-14
申请号：US12707935
申请日：2010-02-18
申请人： Prasanna Sundararajan
发明人： Prasanna Sundararajan
IPC分类号： H03K19/003 , H03K19/007 , G01R31/28
CPC分类号： H03K19/00338 , H03K19/0075 , H03K19/17764
摘要： In one embodiment of the invention, a method is provided for protecting against single event upsets of a circuit in programmable logic. Configuration memory cells of the programmable logic are configured to implement first and second copies of the circuit. In response to detecting a single event upset of one of the configuration memory cells, an address of the one of the configuration memory cells is determined. The one of the first and second copies of the circuit in which the single event upset occurred is determined from the address of the one of the configuration memory cells. The output from the one of the first and second copies of the circuit in which the single event upset did not occur is selected as an output of the circuit.
摘要翻译：在本发明的一个实施例中，提供了一种用于防止在可编程逻辑中的电路的单个事件的不匹配的方法。可编程逻辑的配置存储单元被配置为实现电路的第一和第二副本。响应于检测到一个配置存储器单元的单个事件不正常，确定配置存储器单元之一的地址。发生单次事件不适的电路的第一和第二副本之一由配置存储器单元之一的地址确定。选择其中不发生单事件不正常的电路的第一和第二副本之一的输出作为电路的输出。

16. 发明授权

US07788502B1 Method and system for secure exchange of IP cores 有权
标题翻译： IP核安全交换的方法和系统
公开(公告)号：US07788502B1
公开(公告)日：2010-08-31
申请号：US11076656
申请日：2005-03-10
申请人： Adam P. Donlin , Prasanna Sundararajan , Bernard J. New
发明人： Adam P. Donlin , Prasanna Sundararajan , Bernard J. New
IPC分类号： G06F11/30
CPC分类号： G06F21/76 , G06F2221/2137
摘要： A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.
摘要翻译：公开了一种方法和系统。该系统包括可信任的加载程序。该方法包括将IP核从供应商下载到目标设备。在目标设备处以加密形式接收IP内核，其可以是例如可编程逻辑设备。

17. 发明授权

US07689726B1 Bootable integrated circuit device for readback encoding of configuration data 有权
标题翻译：可引导集成电路设备，用于配置数据的回读编码
公开(公告)号：US07689726B1
公开(公告)日：2010-03-30
申请号：US10956884
申请日：2004-10-01
申请人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
发明人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F3/00 , H03K19/173
CPC分类号： H03K19/17764 , G06F9/4401 , H03K19/17768
摘要： Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.
摘要翻译：描述用于编码配置数据的方法和装置。具有配置接口的集成电路装置耦合到在配置接口处耦合的引导存储器。引导内存包含用于通过配置界面配置集成电路设备的引导内核。引导核心包括配置编码器内核和内部处理器接口核心。引导核心可以进一步包括处理器核心。配置编码器核心提供集成电路设备内部的外围接口，并且引导存储器包含用于对从配置存储器读取的配置数据进行编码的至少一组指令。编码的配置数据可以经由外设接口发送。或者，配置编码器核心可以包括配置比特流，用于在用于编码回读配置数据的可配置资源中实例化编码器。

18. 发明授权

US07343578B1 Method and system for generating a bitstream view of a design 有权
标题翻译：用于生成设计的比特流视图的方法和系统
公开(公告)号：US07343578B1
公开(公告)日：2008-03-11
申请号：US10917064
申请日：2004-08-12
申请人： Cameron D. Patterson , Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan
发明人： Cameron D. Patterson , Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.
摘要翻译：公开了一种用于生成可编程逻辑器件（PLD）设计的位流视图的方法和系统。本发明允许物理电路描述（例如，PLD设计的基本配置位中的一个或多个）与逻辑电路描述（例如，构成PLD设计的一个或多个逻辑元件）的相关性，其中也可以被视为将PLD中设计实现的一个或多个物理元素与设计的一个或多个逻辑元素相关联。

19. 发明授权

US06920627B2 Reconfiguration of a programmable logic device using internal control 有权
公开(公告)号：US06920627B2
公开(公告)日：2005-07-19
申请号：US10377857
申请日：2003-02-28
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F15/78 , H03K19/00 , H03K19/177 , G06F17/50
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

20. 发明授权

US08473880B1 Synchronization of parallel memory accesses in a dataflow circuit 有权
标题翻译：数据流电路中并行存储器访问的同步
公开(公告)号：US08473880B1
公开(公告)日：2013-06-25
申请号：US12791256
申请日：2010-06-01
申请人： David W. Bennett , Prasanna Sundararajan
发明人： David W. Bennett , Prasanna Sundararajan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/74
摘要： Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.
摘要翻译：从高级语言（HLL）规范创建流水线电路设计的方法。在一个实施例中，HLL规范被转换成流水线电路设计的操作的中间级语言规范，并且创建操作的数据依赖图。识别由两个写入操作限定并且在两个写入操作之间没有中间写入操作的操作序列以及序列内的两个或更多个读取操作。从与中级语言规范中的操作相关联的依赖图和硬件组件生成流水线设计规范。对应于两个或多个读取操作的组件中的至少两个组件并行访问存储器，并且对应于两个或多个读取和两个写入操作的每个组件需要同步令牌作为输入，并且在完成时输出同步令牌操作。

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