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1. 发明授权

US08473904B1 Generation of cache architecture from a high-level language description 有权
标题翻译：从高级语言描述生成缓存架构
公开(公告)号：US08473904B1
公开(公告)日：2013-06-25
申请号：US12009272
申请日：2008-01-16
申请人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
发明人： Prasanna Sundararajan , David W. Bennett , Robert G. Dimond , Lauren B. Wenzl , Jeffrey M. Mason
IPC分类号： G06F9/44 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/44 , G06F8/433 , G06F12/00 , G06F13/00 , G06F13/28 , G06F17/5054
摘要： Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.
摘要翻译：描述从高级语言描述生成缓存体系结构。获得了以高级编程语言的应用程序的描述。从适于在硬件中提供实现的描述生成数据流表示。生成包括：识别与描述相关联的存储器的访问; 确定对存储器的至少一部分访问不具有用于本地可缓存数据的一个或多个数据依赖性; 并将该部分分配给分布式高速缓存。

2. 发明授权

US07930662B1 Methods for automatically generating fault mitigation strategies for electronic system designs 有权
标题翻译：自动生成电子系统设计故障缓解策略的方法
公开(公告)号：US07930662B1
公开(公告)日：2011-04-19
申请号：US12264283
申请日：2008-11-04
申请人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
发明人： Prasanna Sundararajan , John D. Corbett , David W. Bennett , Jeffrey M. Mason
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.
摘要翻译：公开了用于产生电子系统设计的方法。在一种方法中，对于设计的第一规范的一个或多个组件中的每一个，响应于与设计的第一规范相关联的用户指定的数据，从多个不同的误差减轻技术中选择错误减轻技术。从第一规格自动生成设计的第二个规范。第二规范包括与针对所述一个或多个组件中的每个组件的每个所选择的误差减轻技术相对应的误差减轻逻辑设计的第二个规格被存储用于后续处理。

3. 发明授权

US09378003B1 Compiler directed cache coherence for many caches generated from high-level language source code 有权
标题翻译：针对高级语言源代码生成的许多缓存的编译器定向缓存一致性
公开(公告)号：US09378003B1
公开(公告)日：2016-06-28
申请号：US12508437
申请日：2009-07-23
申请人： Prasanna Sundararajan , Andrew R. Putnam , Jeffrey M. Mason
发明人： Prasanna Sundararajan , Andrew R. Putnam , Jeffrey M. Mason
IPC分类号： G06F9/45
CPC分类号： G06F8/4441 , G06F8/443 , G06F8/4442 , G06F8/452 , G06F8/454 , G06F8/456
摘要： Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.
摘要翻译：生成和操作电子系统的方法。高级语言（HLL）源代码被编译成等效的中间语言程序代码。编译确定用于存储由HLL源引用的数据的多个高速缓存。刷新指令插入中间语言程序。每个刷新指令引用一个缓存，并且在紧跟在最后写入该缓存的指令之后插入到中间语言程序中。中间语言程序被转换为指定多个高速缓存的硬件描述，用于处理高速缓存中的数据的电路，以及用于每个高速缓存的闪存接口，其响应于刷新而启动从高速缓存向主存储器写入数据信号。基于中间语言程序中的一个或多个刷新指令中的一个的布置来确定各个刷新信号的定时。

4. 发明授权

US08468510B1 Optimization of cache architecture generated from a high-level language description 有权
标题翻译：从高级语言描述生成的缓存架构的优化
公开(公告)号：US08468510B1
公开(公告)日：2013-06-18
申请号：US12508404
申请日：2009-07-23
申请人： Prasanna Sundararajan , Andrew R. Putnam , David W. Bennett
发明人： Prasanna Sundararajan , Andrew R. Putnam , David W. Bennett
IPC分类号： G06F9/45 , G06F13/00 , G06F13/28
CPC分类号： G06F17/505 , G06F17/5054
摘要： Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program. At least one of hardware blocks has access to the multiple consecutively addressed data items in parallel.
摘要翻译：从高级语言（HLL）程序生成硬件规范的方法。在一种方法中，一种方法确定HLL程序中的多个连续寻址数据项的单独访问。 HLL程序被编译成中间语言程序，以包括对多个连续寻址的数据项执行功能的一个或多个指令以及引用连续寻址的数据项的一个或多个存储器访问指令。该方法从中间语言程序生成硬件规范。硬件规范包括高速缓冲存储器，其缓存连续寻址的数据项，并且响应于单个访问请求访问连续寻址的数据项。该规范还包括实现中间语言程序中的指令的功能的一个或多个硬件块。硬件块中的至少一个并行地访问多个连续寻址的数据项。

5. 发明授权

US08473880B1 Synchronization of parallel memory accesses in a dataflow circuit 有权
标题翻译：数据流电路中并行存储器访问的同步
公开(公告)号：US08473880B1
公开(公告)日：2013-06-25
申请号：US12791256
申请日：2010-06-01
申请人： David W. Bennett , Prasanna Sundararajan
发明人： David W. Bennett , Prasanna Sundararajan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/74
摘要： Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.
摘要翻译：从高级语言（HLL）规范创建流水线电路设计的方法。在一个实施例中，HLL规范被转换成流水线电路设计的操作的中间级语言规范，并且创建操作的数据依赖图。识别由两个写入操作限定并且在两个写入操作之间没有中间写入操作的操作序列以及序列内的两个或更多个读取操作。从与中级语言规范中的操作相关联的依赖图和硬件组件生成流水线设计规范。对应于两个或多个读取操作的组件中的至少两个组件并行访问存储器，并且对应于两个或多个读取和两个写入操作的每个组件需要同步令牌作为输入，并且在完成时输出同步令牌操作。

6. 发明授权

US07367007B1 Method of routing a design to increase the quality of the design 有权
标题翻译：路由设计方法以提高设计质量
公开(公告)号：US07367007B1
公开(公告)日：2008-04-29
申请号：US11170408
申请日：2005-06-29
申请人： Prasanna Sundararajan , Carter Hamilton , Ian L. McEwen
发明人： Prasanna Sundararajan , Carter Hamilton , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of circuit design for a programmable logic device (PLD) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the PLD according to, at least in part, the reliability measures. The circuit design for the PLD can be routed using the selected routing resources.
摘要翻译：用于可编程逻辑器件（PLD）的电路设计方法可以包括识别多个路由资源，其中多个路由资源中的每一个与可靠性度量相关联，并且选择路由资源用于路由电路设计至少部分依据PLD的可靠性措施。 PLD的电路设计可以使用选定的路由资源进行路由。

7. 发明授权

US07111215B1 Methods of reducing the susceptibility of PLD designs to single event upsets 有权
标题翻译：降低PLD设计对单次事件的敏感性的方法
公开(公告)号：US07111215B1
公开(公告)日：2006-09-19
申请号：US10768304
申请日：2004-01-29
申请人： Eric R. Keller , Prasanna Sundararajan , Stephen M. Trimberger
发明人： Eric R. Keller , Prasanna Sundararajan , Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： H03K19/00392 , G11C5/063 , G11C11/4125 , H03K19/17736 , H03K19/17764
摘要： Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU affecting one of the duplicate paths simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.
摘要翻译：通过利用大多数PLD设计留下许多路由资源的事实，在可编程逻辑器件（PLD）中实现设计的方法以减少对单事件异常（SEU）的敏感性。未使用的路由资源可用于在设计中的信号的源和目的地之间提供重复的路由路径。选择重复路径使得影响一个重复路径的SEU简单地在两个路径之间切换信号。因此，如果由于SEU而使一个路径被禁用，则另一个路径仍然可以提供必要的连接，并且设计的功能不受影响。该方法可以应用于例如具有由基于静态RAM的配置存储器单元控制的可编程路由多路复用器的现场可编程门阵列（FPGA）的路由软件。

8. 发明授权

US06668237B1 Run-time reconfigurable testing of programmable logic devices 有权
标题翻译：可编程逻辑器件的运行时可重构测试
公开(公告)号：US06668237B1
公开(公告)日：2003-12-23
申请号：US10052720
申请日：2002-01-17
申请人： Steven A. Guccione , Prasanna Sundararajan , Scott P. McMillan
发明人： Steven A. Guccione , Prasanna Sundararajan , Scott P. McMillan
IPC分类号： G01R2728
CPC分类号： G01R31/318516
摘要： Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.
摘要翻译：用于测试可编程逻辑器件（PLD）电路的方法和系统。主机数据处理装置配置有运行时重配置编程接口，并且在主机装置上执行调用接口的方法的运行时重配置测试程序。响应于从测试程序调用的编程接口的方法，PLD配置有第一配置比特流。响应于从测试程序调用的编程接口的方法，从PLD读回状态数据。测试程序还识别状态数据和预期结果数据之间的差异。

9. 发明授权

US06530071B1 Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable cores 有权
标题翻译：用于使用运行时可参数化的内核来容忍可编程逻辑器件中的缺陷的方法和装置
公开(公告)号：US06530071B1
公开(公告)日：2003-03-04
申请号：US09676298
申请日：2000-09-28
申请人： Steven A. Guccione , Prasanna Sundararajan
发明人： Steven A. Guccione , Prasanna Sundararajan
IPC分类号： G06F1750
CPC分类号： G06F11/142 , G06F17/5054
摘要： Method and apparatus for tolerating defects in a programmable logic device (PLD). A PLD includes a plurality of configurable logic elements and interconnect resources, wherein one or more of the configurable logic elements and interconnect resources have circuit defects. A design program is executed that is suitable for run-time reconfiguration of the PLD. The design program includes executable code that specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and interconnect resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter.
摘要翻译：用于容许可编程逻辑器件（PLD）中的缺陷的方法和装置。 PLD包括多个可配置逻辑元件和互连资源，其中一个或多个可配置逻辑元件和互连资源具有电路缺陷。执行适合PLD的运行时重新配置的设计程序。设计程序包括指定电路设计的可执行代码，并生成在可编程逻辑器件上实现电路设计的配置位流。设计程序还包括有选择地跳过可配置逻辑元件并互连包含缺陷的资源的代码。在各种实施例中，可以响应于输入参数跳过单个可配置逻辑元件，整行或整列元素。

10. 发明授权

US07519823B1 Concealed, non-intrusive watermarks for configuration bitstreams 有权
标题翻译：隐藏的非侵入式水印用于配置比特流
公开(公告)号：US07519823B1
公开(公告)日：2009-04-14
申请号：US10917042
申请日：2004-08-12
申请人： Paul R. Schumacher , Robert D. Turney , Mark Paluszkiewicz , Prasanna Sundararajan , Brandon J. Blodget
发明人： Paul R. Schumacher , Robert D. Turney , Mark Paluszkiewicz , Prasanna Sundararajan , Brandon J. Blodget
IPC分类号： H04L9/00
CPC分类号： G06F21/76 , G06F21/16 , H04L9/0662 , H04L2209/12 , H04L2209/16 , H04L2209/608
摘要： Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.
摘要翻译：公开了用于在可编程逻辑器件（PLD）的配置比特流中嵌入标识符信息的各种方法。在各种实施例中，识别在实现设计时未使用的配置比特流中的比特。标识符信息被加密，并且使用伪随机函数来选择未使用位的子集。加密的标识符信息被放置在所选未使用的子集的子集中。解密是通过逆转加密方法来实现的。

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