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11. 发明申请

US20070038865A1 TAMPER-PROOF CAPS FOR LARGE ASSEMBLY 失效
标题翻译：用于大型组装的防篡改剂
公开(公告)号：US20070038865A1
公开(公告)日：2007-02-15
申请号：US11460329
申请日：2006-07-27
申请人： Stefano Oggioni , Vincenzo Condorelli , Nihad Hadzic
发明人： Stefano Oggioni , Vincenzo Condorelli , Nihad Hadzic
IPC分类号： H04L9/00
CPC分类号： G06F21/87 , H01L23/576 , H01L2224/16225 , H01L2924/15156 , H01L2924/3025 , H05K1/0275 , H05K1/141 , H05K2201/0715 , H05K2201/10151 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49172 , Y10T29/49174
摘要： A tamper-proof cap adapted to be mounted on a large assembly for shielding a selected area of the large assembly is disclosed. The tamper-proof cap comprises a laminate stack-up structure wherein at least one open chamber is formed. The stack-up structure comprises at least two layers wherein tamper-proof layers are formed on top of the open chamber. A plurality of vias are disposed around the open chamber, forming with said tamper proof layers a tamper-proof structure around said open chamber. The vias are adapted for connecting the tamper-proof layers to the large assembly when the tamper-proof cap is mounted. In a preferred embodiment, the tamper-proof cap further comprises a shielding layer on top of the tamper-proof layer that are preferably done using conductive ink.
摘要翻译：公开了一种适于安装在大型组件上用于屏蔽大组件的选定区域的防篡改盖。防破坏盖包括层压叠层结构，其中形成至少一个开放室。堆叠结构包括至少两层，其中在敞开室的顶部上形成防篡改层。多个通孔设置在开放室周围，与所述防篡改层一起形成围绕所述开放室的防篡改结构。当安装防盗盖时，通孔适于将防篡改层连接到大组件。在优选实施例中，防篡改帽还包括防篡改层顶部的屏蔽层，其优选地使用导电油墨进行。

12. 发明申请

US20060288574A1 COAXIAL VIA STRUCTURE FOR OPTIMIZING SIGNAL TRANSMISSION IN MULTIPLE LAYER ELECTRONIC DEVICE CARRIERS 失效
标题翻译：同轴通过多层电子设备载波优化信号传输的结构
公开(公告)号：US20060288574A1
公开(公告)日：2006-12-28
申请号：US11458727
申请日：2006-07-20
申请人： Stefano Oggioni , Gianluca Rogiani , Mauro Spreafico , Giorgio Viero
发明人： Stefano Oggioni , Gianluca Rogiani , Mauro Spreafico , Giorgio Viero
IPC分类号： H01K3/10
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01P1/047 , H01P3/06 , H05K1/0222 , H05K1/0251 , H05K1/115 , H05K3/429 , H05K3/4602 , H05K2201/09618 , H05K2201/09627 , H05K2201/09809 , Y10T29/49117 , Y10T29/49126 , Y10T29/49165 , H01L2924/00
摘要： A coaxial via structure is adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.
摘要翻译：同轴通孔结构适于通过电子设备载体的导电层传输高速信号或高强度电流。同轴通孔结构包括中心导电轨道和由电介质材料隔开的外部导电轨道，并且位于电子设备载体的芯部或电子设备的整个厚度中。同轴通孔结构可以与堆叠的通孔结构组合，以便当制造过程限制整个电子设备载体上完整的同轴通孔结构的创建时，允许跨越电子设备载体的高速信号的有效传输。

13. 发明申请

US20060011712A1 IMPROVED DECAL SOLDER TRANSFER METHOD 审中-公开
标题翻译：改进的分解焊接转移方法
公开(公告)号：US20060011712A1
公开(公告)日：2006-01-19
申请号：US11160887
申请日：2005-07-14
申请人： Stefano Oggioni
发明人： Stefano Oggioni
IPC分类号： B23K31/02 , B23K35/12
CPC分类号： H01L21/6835 , B23K3/0623 , B23K2101/40 , B81C1/0038 , B81C2201/0197 , B81C2203/035 , H01L24/11 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/11003 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H05K3/3478 , H05K2203/0113 , H05K2203/0338 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method is provided for forming alloy deposits at selected areas on a receiving substrate, including providing a decal alloy carrier, having alloy loadable areas in selected positions thereof, the alloy loadable areas being adapted to being loaded with an alloy mass, mating the decal alloy carrier with the receiving substrate, so that the alloy loadable areas substantially correspond to the selected areas on the receiving substrate, and reflowing the solder alloy masses so as to cause transfer of the alloy from the alloy loadable areas to selected areas on the receiving substrate, such as solder-affine pads, while ensuring that the decal alloy carrier and the receiving substrate are kept in close contact one to another at least during the reflowing. The alloy loadable areas are preferrably recesses in the decal alloy carrier having flat bottoms, which results in relaxed alignment tolerances.
摘要翻译：提供了一种用于在接收基板上的选定区域形成合金沉积物的方法，包括提供具有在其选定位置的合金可加载区域的贴花合金载体，合金可装载区域适于装载合金块，将该贴花合金载体与接收基板接合，使得合金可加载区域基本上对应于接收基板上的选定区域，并且回流焊料合金块，以使合金从合金可加载区域转移到接收基板上的选定区域，例如焊锡焊盘，同时确保贴合合金载体和接收基板至少在回流期间彼此保持紧密接触。合金可加载区域在具有平坦底部的贴花合金载体中优选为凹陷，这导致松弛的对准公差。

14. 发明申请

US20050167811A1 MODULE POWER DISTRIBUTION NETWORK 失效
标题翻译：模块电力分配网络
公开(公告)号：US20050167811A1
公开(公告)日：2005-08-04
申请号：US10906152
申请日：2005-02-04
申请人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
发明人： Roland Frech , Bernd Garben , Erich Klink , Stefano Oggioni
IPC分类号： H01L23/12 , H01L23/498 , H05K1/00 , H05K1/02 , H01L23/495
CPC分类号： H05K1/0216 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/09701 , H01L2924/15192 , H01L2924/19105 , H01L2924/3011 , H05K1/0231 , H05K1/0298 , H05K2201/09327 , H05K2201/10522 , H05K2201/10734
摘要： A multi-layer module for packaging an electronic component comprises an uppermost electrically conductive layer for mounting the component, a plurality of electrically insulative layers, and a plurality of electrically conductive layers disposed between the insulative layers. The electrically conductive layers form staggered placements of at least three voltage and/or ground distribution layers close to the module surface without signal wiring layers in between, and signal distribution layers comprising signal conductors. Vias form conductive paths through the insulative layers and conductive layers; the corresponding signal, voltage and ground distribution layers are electrically connected with each other and with the uppermost layer.
摘要翻译：用于封装电子部件的多层模块包括用于安装部件的最上层的导电层，多个电绝缘层以及设置在绝缘层之间的多个导电层。导电层在靠近模块表面的至少三个电压和/或接地分布层之间形成交错布置，而其间不包括信号布线层，以及包括信号导体的信号分布层。通孔形成穿过绝缘层和导电层的导电路径; 相应的信号，电压和地面分布层彼此电连接并与最上层电连接。

15. 发明申请

US20080020600A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
公开(公告)号：US20080020600A1
公开(公告)日：2008-01-24
申请号：US11865293
申请日：2007-10-01
申请人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
发明人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
IPC分类号： H01R12/14
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

16. 发明申请

US20080020599A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
公开(公告)号：US20080020599A1
公开(公告)日：2008-01-24
申请号：US11865253
申请日：2007-10-01
申请人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
发明人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
IPC分类号： H01R12/04 , H05K3/36
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

17. 发明申请

US20080011814A1 Method and System for Self-Aligning Parts in Mems 审中-公开
标题翻译：内存中自动对齐零件的方法和系统
公开(公告)号：US20080011814A1
公开(公告)日：2008-01-17
申请号：US10596349
申请日：2004-11-08
申请人： Stefano Oggioni , Thomas Albrecht , Michel Despont , Mark Lantz , Michele Castriotta
发明人： Stefano Oggioni , Thomas Albrecht , Michel Despont , Mark Lantz , Michele Castriotta
IPC分类号： B23K31/02 , B81B7/00
CPC分类号： B81C3/002 , H05K3/3436 , H05K2201/094 , H05K2201/09418 , H05K2201/2036 , H05K2203/048 , Y02P70/613
摘要： A method and system for efficiently self-aligning parts of a MEMS during manufacturing, as well as controlling distance between these parts, are disclosed. According to the invention each MEMS part comprises at least one pad that is aligned so as to form a pair of pads. In a preferred embodiment, each part comprises three pads. The pad shape of two pairs of pads is rectangular, one pair being rotated of an angle approximately equal to 90° from the other, and the pad shape of the third pair is annular. Therefore, one of the pair of pads allows alignment according to a first direction, a second pair of pads allows alignment according to a second direction, and the third pair of pads allows rotational alignment.
摘要翻译：公开了一种用于在制造期间有效地对准MEMS部件的方法和系统，以及控制这些部件之间的距离。根据本发明，每个MEMS部件包括至少一个对准以形成一对焊盘的焊盘。在优选实施例中，每个部分包括三个焊盘。两对焊盘的焊盘形状是矩形的，一对由另一对旋转大约等于90°的角度，第三对的焊盘形状是环形的。因此，一对衬垫之一允许根据第一方向进行对准，第二对衬垫允许根据第二方向对准，并且第三对衬垫允许旋转对准。

18. 发明申请

US20060008970A1 OPTIMIZED PLATING PROCESS FOR MULTILAYER PRINTED CIRCUIT BOARDS HAVING EDGE CONNECTORS 审中-公开
标题翻译：具有边缘连接器的多层印刷电路板优化镀层工艺
公开(公告)号：US20060008970A1
公开(公告)日：2006-01-12
申请号：US11160780
申请日：2005-07-08
申请人： Stefano Oggioni , Giorgio Viero
发明人： Stefano Oggioni , Giorgio Viero
IPC分类号： H01L21/8238
CPC分类号： H05K3/244 , H05K1/117 , H05K3/243 , H05K2201/0391 , H05K2203/054 , H05K2203/058 , H05K2203/072 , H05K2203/0723
摘要： A process for manufacturing printed wire boards with hard plated sliding contact tabs and soft plated wire bond pads. Sliding contact tabs are covered by a protective coating after being hard plated thus allowing the soft plating of wire bond pads without damaging the hard plated sliding contact tabs. In a preferred embodiment, the hard plating includes the step of electroplating nickel on the sliding contact tabs, followed by electroplating an alloy of gold and cobalt, using standard electroplating process. An electro-less soft plating process includes the steps of plating a nickel layer on the wire bond pads and then a gold layer after having “flash-etched” the copper seeding.
摘要翻译：一种制造具有硬镀滑动接触片和软电镀线接合垫的印刷线路板的方法。硬接触后，滑动接触片被保护层覆盖，从而允许电焊接焊盘的软电镀，而不会损坏硬镀滑动接触片。在优选实施例中，硬镀层包括在滑动接触片上电镀镍的步骤，然后使用标准电镀工艺电镀金和钴的合金。无电镀软工艺包括以下步骤：在铜接合焊盘上镀镍层，然后在“闪光蚀刻”铜接种之后镀金层。

19. 发明申请

US20050001017A1 WATER SOLUBLE PROTECTIVE PASTE FOR MANUFACTURING PRINTED CIRCUIT BOARDS 失效
标题翻译：用于制造印刷电路板的水溶性保护胶
公开(公告)号：US20050001017A1
公开(公告)日：2005-01-06
申请号：US10707724
申请日：2004-01-07
申请人： Stefano Oggioni
发明人： Stefano Oggioni
IPC分类号： H05K3/28 , B23K31/00
CPC分类号： H05K3/282 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H05K3/1275 , H05K2203/049 , H05K2203/0534 , H05K2203/0786 , H01L2924/00
摘要： An improved water soluble protective paste and a method for protecting metal circuits and pads on the surface of an electronic board during the manufacturing steps. A densifier is added to the paste making it easier and more efficient the dispensing of the paste. After deposition the layer is dried until a solid protective film is obtained. An additional advantage obtained by the present invention is that the protective layer can be deposited also by means of an offset printing process, avoiding the use of the stencil and of the screening steps. Screening process is a labourious operation which requires very sophisticated equipment and a very high precision in the design of the stencil. Because of these requirements, screening is an expensive process. On the other hand offset printing is a very simple, cheap and reliable method. In addition, the film forming properties allow the material to create a protective film even with a thin deposited film.
摘要翻译：改进的水溶性保护膏和在制造步骤期间保护电子板表面上的金属电路和焊盘的方法。将增稠剂添加到糊料中，使糊剂分配更容易和更有效。沉积后，将层干燥直到得到固体保护膜。通过本发明获得的另外的优点是保护层也可以通过胶版印刷工艺沉积，避免使用模版和筛选步骤。筛选过程是一项精心的操作，需要非常精密的设备和极高的模具设计精度。由于这些要求，筛选是一个昂贵的过程。另一方面，胶印是一种非常简单，便宜可靠的方法。此外，成膜性能即使用薄的沉积膜也能够使材料形成保护膜。

20. 发明授权

US06717255B2 Chip carrier for a high-frequency electronic package 有权
标题翻译：用于高频电子封装的芯片载体
公开(公告)号：US06717255B2
公开(公告)日：2004-04-06
申请号：US10032675
申请日：2001-10-23
申请人： Stefano Oggioni , Roberto Ravanelli
发明人： Stefano Oggioni , Roberto Ravanelli
IPC分类号： H01L2348
CPC分类号： H01L23/552 , H01L23/49816 , H01L23/66 , H01L2224/48091 , H01L2924/01322 , H01L2924/15173 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014
摘要： An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal. The chip carrier further includes a reference structure having at least two conductive layers such that the signal track is electrically shielded by the reference structure. A semiconductor chip is positioned on the chip carrier and includes at least one terminal electrically interconnected to the at least one contact area.
摘要翻译：提供电子包装。电子封装包括具有第一导电层的芯片载体，所述第一导电层包括至少一个信号轨道和至少一个接触区域，所述接触区域电连接到所述信号轨道并适于发射高频信号。芯片载体还包括具有至少两个导电层的参考结构，使得信号轨道被参考结构电屏蔽。半导体芯片位于芯片载体上，并且包括至少一个电连接到至少一个接触区域的端子。

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