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1. 发明申请

US20080222430A1 Protection of Secure Electronic Modules Against Attacks 失效
标题翻译：保护安全电子模块免受攻击
公开(公告)号：US20080222430A1
公开(公告)日：2008-09-11
申请号：US11682349
申请日：2007-03-06
申请人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
发明人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
IPC分类号： G06F12/14
CPC分类号： G06F21/86 , G06F2221/2143
摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn in secure electronic modules. Sequentially storing the data, and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.
摘要翻译：公开了一种用于防止在安全电子模块中由优选状态/烧伤引起的秘密数据的意外保留的方法和装置。顺序存储数据及其在交替时钟周期上的反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销擦除较大的存储区域。

2. 发明申请

US20070255966A1 Cryptographic circuit with voltage-based tamper detection and response circuitry 审中-公开
标题翻译：具有基于电压的篡改检测和响应电路的加密电路
公开(公告)号：US20070255966A1
公开(公告)日：2007-11-01
申请号：US11416005
申请日：2006-05-01
申请人： Vincenzo Condorelli , Kevin Gotze , Nihad Hadzic
发明人： Vincenzo Condorelli , Kevin Gotze , Nihad Hadzic
IPC分类号： G06F12/14
CPC分类号： G06F21/87
摘要： A cryptographic circuit with voltage island-based tamper detection and response is disclosed. The circuit includes a voltage island having at least one monitoring circuit and a first storage area for security parameters. The circuit also includes a second storage area for key storage and management logic to tamper the security parameters upon detection of an environmental failure.
摘要翻译：公开了一种具有电压岛式篡改检测和响应的加密电路。电路包括具有至少一个监控电路的电压岛和用于安全参数的第一存储区域。电路还包括用于密钥存储和管理逻辑的第二存储区域，用于在检测到环境故障时篡改安全参数。

3. 发明授权

US06556495B2 2-D FIFO memory having full-width read/write capability 失效
标题翻译：具有全宽读/写能力的2-D FIFO存储器
公开(公告)号：US06556495B2
公开(公告)日：2003-04-29
申请号：US09901864
申请日：2001-07-09
申请人： Vincenzo Condorelli , Nihad Hadzic
发明人： Vincenzo Condorelli , Nihad Hadzic
IPC分类号： G11C700
CPC分类号： G06F5/10 , G06F5/065
摘要： An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.
摘要翻译：公开了一种用于在由排列成行和列的多个存储单元组成的FIFO存储器阵列中选择数据的装置和方法，其中每行单元具有可选地由相关行地址可寻址的相关联的字线数，单元格列具有相关联的位线，其提供对由相应字线启用的关联列的存储器单元的访问; 并且存储器阵列包括地址解码器，其具有地址输入，用于根据输入地址接收用于选择字线的输入地址;以及可编程宽度垂直指示器，用于向地址解码器的地址输入提供读和写输入地址在存储器阵列的相关读取和写入操作期间，其中可编程宽度的垂直指示器在存储器阵列的操作期间修改读取和写入地址并提供FIFO存储器功能。

4. 发明授权

US08903966B2 Re-programming programmable hardware devices without system downtime 有权
公开(公告)号：US08903966B2
公开(公告)日：2014-12-02
申请号：US13151079
申请日：2011-06-01
申请人： Carl A. Bender , Nihad Hadzic , Jeffrey C. Hanscom , Howard M. Haynie , Jeffrey M. Turner
发明人： Carl A. Bender , Nihad Hadzic , Jeffrey C. Hanscom , Howard M. Haynie , Jeffrey M. Turner
IPC分类号： G06F9/445 , G06F15/78 , G06F9/44
CPC分类号： G06F8/665 , G06F8/654 , G06F9/4418 , G06F15/7871 , G06F15/7892
摘要： Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

5. 发明授权

US07689292B2 Nerve stimulation functionality indicator apparatus and method 有权
标题翻译：神经刺激功能指示仪及方法
公开(公告)号：US07689292B2
公开(公告)日：2010-03-30
申请号：US10375678
申请日：2003-02-27
申请人： Admir Hadzic , Alen Hadzic , Nihad Hadzic , Giglioli Sergio , Franca Gelatti, legal representative , Jerry Vloka , Howard Donnelly
发明人： Admir Hadzic , Alen Hadzic , Nihad Hadzic , Giglioli Sergio , Jerry Vloka , Howard Donnelly
IPC分类号： A61N1/00 , A61B5/05 , A61B18/18
CPC分类号： A61N1/37282 , A61N1/0551 , A61N1/36021 , A61N1/37247
摘要： An operational status display for a nerve stimulator is located remote from the nerve stimulator. In one embodiment the display comprises a stand-alone discrete component that can be placed as desired by the nerve stimulator needle. In another embodiment, the display comprises an integral part of the nerve stimulator needle. The display can be alphanumeric or can comprise one or more discrete signal lights or other visual indicia. Color can be used to provide information regarding levels (intensity) of current, or the energy being provided to the needle and/or being delivered to the patient. In some embodiments these displays also provide information regarding the presence or absence of current and/or the polarity of the electricity then being provided to the nerve stimulator needle.
摘要翻译：神经刺激器的操作状态显示位于远离神经刺激器的位置。在一个实施例中，显示器包括可以由神经刺激器针根据需要放置的独立离散部件。在另一个实施例中，显示器包括神经刺激器针的整体部分。显示器可以是字母数字的或可以包括一个或多个离散信号灯或其他视觉标记。可以使用颜色来提供关于电流的水平（强度）或提供给针的能量和/或被递送给患者的信息。在一些实施例中，这些显示器还提供关于电神经刺激器针的电流和/或极性的存在或不存在的信息。

6. 发明申请

US20070038865A1 TAMPER-PROOF CAPS FOR LARGE ASSEMBLY 失效
标题翻译：用于大型组装的防篡改剂
公开(公告)号：US20070038865A1
公开(公告)日：2007-02-15
申请号：US11460329
申请日：2006-07-27
申请人： Stefano Oggioni , Vincenzo Condorelli , Nihad Hadzic
发明人： Stefano Oggioni , Vincenzo Condorelli , Nihad Hadzic
IPC分类号： H04L9/00
CPC分类号： G06F21/87 , H01L23/576 , H01L2224/16225 , H01L2924/15156 , H01L2924/3025 , H05K1/0275 , H05K1/141 , H05K2201/0715 , H05K2201/10151 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49172 , Y10T29/49174
摘要： A tamper-proof cap adapted to be mounted on a large assembly for shielding a selected area of the large assembly is disclosed. The tamper-proof cap comprises a laminate stack-up structure wherein at least one open chamber is formed. The stack-up structure comprises at least two layers wherein tamper-proof layers are formed on top of the open chamber. A plurality of vias are disposed around the open chamber, forming with said tamper proof layers a tamper-proof structure around said open chamber. The vias are adapted for connecting the tamper-proof layers to the large assembly when the tamper-proof cap is mounted. In a preferred embodiment, the tamper-proof cap further comprises a shielding layer on top of the tamper-proof layer that are preferably done using conductive ink.
摘要翻译：公开了一种适于安装在大型组件上用于屏蔽大组件的选定区域的防篡改盖。防破坏盖包括层压叠层结构，其中形成至少一个开放室。堆叠结构包括至少两层，其中在敞开室的顶部上形成防篡改层。多个通孔设置在开放室周围，与所述防篡改层一起形成围绕所述开放室的防篡改结构。当安装防盗盖时，通孔适于将防篡改层连接到大组件。在优选实施例中，防篡改帽还包括防篡改层顶部的屏蔽层，其优选地使用导电油墨进行。

7. 发明授权

US08683307B2 Checksum calculation, prediction and validation 失效
标题翻译：校验和计算，预测和验证
公开(公告)号：US08683307B2
公开(公告)日：2014-03-25
申请号：US13117294
申请日：2011-05-27
申请人： Carl A. Bender , Michael J. Cardigan, Jr. , Nihad Hadzic , Howard M. Haynie , Jeffrey M. Turner , Raymond Wong
发明人： Carl A. Bender , Michael J. Cardigan, Jr. , Nihad Hadzic , Howard M. Haynie , Jeffrey M. Turner , Raymond Wong
IPC分类号： G06F11/00
CPC分类号： H03M13/096 , G06F11/1004
摘要： A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.
摘要翻译：校验和计算，预测和验证系统包括主机系统，网络接口，布置在主机系统和网络接口之间的接收管线，并且被配置为计算与在主机系统中接收的分组相关的预期的完整校验和以及设置在主机系统之间的传输管线主机系统和网络接口，并配置计算与数据包相关的因素，用于传输网络接口。

8. 发明申请

US20120311110A1 RE-PROGRAMMING PROGRAMMABLE HARDWARE DEVICES WITHOUT SYSTEM DOWNTIME 有权
标题翻译：不编程可编程硬件设备，无系统停机
公开(公告)号：US20120311110A1
公开(公告)日：2012-12-06
申请号：US13151079
申请日：2011-06-01
申请人： Carl A. Bender , Nihad Hadzic , Jeffrey C. Hanscom , Howard M. Haynie , Jeffrey M. Turner
发明人： Carl A. Bender , Nihad Hadzic , Jeffrey C. Hanscom , Howard M. Haynie , Jeffrey M. Turner
IPC分类号： G06F15/177 , G06F9/00
CPC分类号： G06F8/665 , G06F8/654 , G06F9/4418 , G06F15/7871 , G06F15/7892
摘要： Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.
摘要翻译：可编程硬件设备经过重新编程，无需系统停机。要重新编程设备，设备静止，与设备关联的状态保存，更新加载，状态恢复，操作恢复，对系统都是透明的，除了系统可能的延迟。

9. 发明申请

US20120300790A1 MEMORY SAVING PACKET MODIFICATION 有权
标题翻译：内存节省包修改
公开(公告)号：US20120300790A1
公开(公告)日：2012-11-29
申请号：US13117345
申请日：2011-05-27
申请人： Michael J. Cadigan, JR. , Nihad Hadzic , Jeffrey M. Turner , Raymond Wong
发明人： Michael J. Cadigan, JR. , Nihad Hadzic , Jeffrey M. Turner , Raymond Wong
IPC分类号： H04J3/24
CPC分类号： H04L69/22 , H04L43/02 , H04L43/04
摘要： The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.
摘要翻译：该方法包括为数据传输事件的所有分组创建报头的主副本，主副本包括多个完整的常数报头信息，多个完整的常数报头信息对于数据传输事件的所有分组是恒定的，存储数据传输事件的所有数据包的唯一标题信息，唯一标题信息包括数据传输事件的至少一个数据包唯一的信息，标记数据传输事件的每个数据包的标识，以创建每个数据包的标记化数据包ID，并基于标记化索引存储的唯一标题信息。一种用于引导计算机处理器执行方法的计算机程序产品。根据该方法，在分组读取时，与分组相关联的唯一报头信息被覆盖在主副本上以创建唯一分组。

10. 发明授权

US07953987B2 Protection of secure electronic modules against attacks 失效
标题翻译：保护安全的电子模块免受攻击
公开(公告)号：US07953987B2
公开(公告)日：2011-05-31
申请号：US11682349
申请日：2007-03-06
申请人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
发明人： Carl U. Buscaglia , Vincenzo Condorelli , Kevin C. Gotze , Nihad Hadzic , Donald W. Plass , Tamas Visegrady
IPC分类号： G06F12/14
CPC分类号： G06F21/86 , G06F2221/2143
摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.
摘要翻译：公开了一种用于防止由安全电子模块中的优选状态/老化引起的秘密数据的意外保留的方法和装置。在交替的时钟周期内顺序存储数据及其反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销擦除较大的存储区域。

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