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11. 发明授权

US5316969A Method of shallow junction formation in semiconductor devices using gas immersion laser doping 失效
标题翻译：使用气浸式激光掺杂的半导体器件中浅结形成的方法
公开(公告)号：US5316969A
公开(公告)日：1994-05-31
申请号：US993788
申请日：1992-12-21
申请人： Emi Ishida , Thomas W. Sigmon , William T. Lynch
发明人： Emi Ishida , Thomas W. Sigmon , William T. Lynch
IPC分类号： H01L21/00 , H01L21/223 , H01L21/225 , H01L21/3215
CPC分类号： H01L21/67253 , H01L21/223 , H01L21/2252 , H01L21/2257 , H01L21/32155 , Y10S148/129
摘要： Shallow regions are formed in a semiconductor body by irradiating the surface region with a pulsed laser beam in an atmosphere including the dopant. The pulsed laser beam has sufficient intensity to drive in dopant atoms from the atmosphere but insufficient intensity to melt the semiconductor material. A silicide layer can be placed over the surface of the semiconductor material prior to irradiation with the dopant being driven from the atmosphere through the silicide into the surface region of the semiconductor body. Alternatively, the silicide layer can include dopant atoms prior to irradiating the surface region.
摘要翻译：通过在包括掺杂剂的气氛中用脉冲激光束照射表面区域，在半导体本体中形成浅区域。脉冲激光束具有足够的强度来驱动来自大气的掺杂剂原子，但不足以使半导体材料熔化。在辐照之前，硅化物层可以放置在半导体材料的表面上，掺杂剂通过硅化物从大气驱动到半导体本体的表面区域。或者，硅化物层可以在照射表面区域之前包括掺杂剂原子。

12. 发明授权

US5304834A Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets 失效
标题翻译：在二氧化硅孔隙中硅的选择性外延，抑制不需要的刻面形成
公开(公告)号：US5304834A
公开(公告)日：1994-04-19
申请号：US6094
申请日：1993-01-15
申请人： William T. Lynch
发明人： William T. Lynch
IPC分类号： H01L21/20 , H01L21/336 , H01L21/76 , H01L21/762 , H01L29/78 , H01L27/01 , H01L27/13 , H01L29/18
CPC分类号： H01L21/76294 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： In the prior art, selective epitaxial growth (SEG) of semiconductors, performed typically in rectangular windows penetrating through a masking layer located on a major surface of semiconductor substrate, suffers from unwanted facet formation at the corners of the windows--whereby the desirable planar area available for transistor fabrication is reduced. Such facet formation is suppressed--i.e., the area occupied by unwanted facets is reduced--by adding a relatively small lobe penetrating through the masking layer at each corner of each window prior to performing the SEG, whereby transistor packing density can be increased.
摘要翻译：在现有技术中，半导体的选择性外延生长（SEG）通常在贯穿位于半导体衬底的主表面上的掩模层的矩形窗中进行，在窗口的拐角处遭受不想要的小面形成 - 从而所需的平面面积可用于晶体管制造减少。通过在执行SEG之前，通过在每个窗口的每个角落处穿过穿透掩模层的相对较小的波瓣来减小这种小面形成 - 即，由不想要的刻面占据的面积减小，从而可以增加晶体管堆积密度。

13. 发明授权

US5057455A Formation of integrated circuit electrodes 失效
标题翻译：集成电路电极的形成
公开(公告)号：US5057455A
公开(公告)日：1991-10-15
申请号：US443766
申请日：1989-11-30
申请人： Pang-Dow Foo , William T. Lynch , Chien-Shing Pai
发明人： Pang-Dow Foo , William T. Lynch , Chien-Shing Pai
IPC分类号： H01L29/73 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/331 , H01L21/762 , H01L21/768 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/76802 , H01L21/28525 , H01L21/31144 , H01L21/32139 , H01L21/762 , H01L21/8249 , Y10S438/97
摘要： In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors. In addition, both the source and drain electrodes of the MOS transistors and the base electrodes of the bipolar transistors can then be simultaneously formed in a self-aligned manner without the need for etching into the underlying semiconductor substrate in which the integrated circuit is being formed.
摘要翻译：在BiCMOS集成电路中用于晶体管的电极的制造中，在位于相对较薄的多晶硅层上的相对较厚的TEOS（或其它合适的电介质）层中蚀刻的垂直窗口依次位于相对锡氧化物层区域上并且相对较厚氧化物层区域用于限定保留多晶硅电极材料的区域。多晶硅沉积在相对厚的绝缘层中的窗口中，以形成每个窗口中所需电极的基础。此后，在相对较厚的电介质层的去除期间，相对薄的多晶硅层（或者可选地，α-非晶硅层）被用作蚀刻停止层。此后，可以使用窗口来制造MOS和双极晶体管，以限定MOS晶体管的栅极区域的范围和双极晶体管的发射极区域的范围。此外，MOS晶体管的源电极和漏电极以及双极晶体管的基极可以以自对准的方式同时形成，而不需要蚀刻到其中形成集成电路的下面的半导体衬底。

14. 发明授权

US4914500A Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices 失效
标题翻译：用于制造包括具有含金属材料区域的源极和漏极的半导体器件的方法以及所得到的器件
公开(公告)号：US4914500A
公开(公告)日：1990-04-03
申请号：US128742
申请日：1987-12-04
申请人： Ruichen Liu , William T. Lynch , David S. Williams
发明人： Ruichen Liu , William T. Lynch , David S. Williams
IPC分类号： H01L29/78 , H01L21/225 , H01L21/28 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/812
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/823814 , H01L27/0928 , H01L2924/0002 , Y10S148/019
摘要： A new method for fabricating a semiconductor device, e.g., a MOS or MES IC, as well as the resulting device, are disclosed. In accordance with the new method, a semiconductor device is formed, at least in part, by forming a material region which includes metal, e.g., elemental metal or a metal-containing compound, on a semiconductor substrate. One or more dopants are implanted into the material region, and the substrate is heated in order to diffuse the dopants out of the material region and into the substrate, thus forming a dopant-diffused substrate region, e.g., a source or drain. Significantly, the new method involves implant conditions which yield a material region-to-substrate specific contact resistance equal to or less than about 10.sup.-6 .OMEGA.-cm.sup.2. In addition, the new method involves heating temperatures and heating times which yield a dopant-diffused substrate region having a depth, relative to the top of the material region, equal to or less than about 0.2 micrometers.

15. 发明授权

US4825278A Radiation hardened semiconductor devices 失效
标题翻译：辐射硬化半导体器件
公开(公告)号：US4825278A
公开(公告)日：1989-04-25
申请号：US20771
申请日：1987-03-02
申请人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
发明人： Steven J. Hillenius , William T. Lynch , Lalita Manchanda
IPC分类号： H01L21/765 , H01L23/58 , H01L23/60 , H01L29/06 , H01L29/40
CPC分类号： H01L29/402 , H01L21/765 , H01L23/585 , H01L23/60 , H01L2924/0002 , Y10S257/906
摘要： Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.
摘要翻译：公开了对辐射效应高度耐受的半导体器件和电路。在器件的通常的场氧化物下方设置偏置于衬底电位的薄导电层和薄氧化物。由于辐射吸收，导电层屏蔽半导体衬底免受场氧化物中的电荷产生的影响。

16. 发明授权

US4665414A Schottky-barrier MOS devices 失效
标题翻译：肖特基势垒MOS器件
公开(公告)号：US4665414A
公开(公告)日：1987-05-12
申请号：US820597
申请日：1986-01-21
申请人： Conrad J. Koeneke , Martin P. Lepselter , William T. Lynch
发明人： Conrad J. Koeneke , Martin P. Lepselter , William T. Lynch
IPC分类号： H01L21/266 , H01L21/285 , H01L21/336 , H01L27/092 , H01L29/10 , H01L29/47 , H01L29/78 , H01L29/48 , H01L23/48
CPC分类号： H01L21/28537 , H01L21/266 , H01L27/092 , H01L29/1087 , H01L29/47 , H01L29/66643 , H01L29/7839 , Y10S257/902
摘要： Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).
摘要翻译：通过选择性掺杂围绕肖特基势垒源极和漏极触点的区域，肖特基势垒MOS和CMOS器件得到显着改善。对于p沟道器件，受体掺杂以一步或两步离子注入法进行。对于n沟道器件，施主掺杂是以两步法进行的。在每种情况下，电流注入到通道中都会增强，并且对基板的泄漏减小，同时仍然保持对寄生双极晶体管作用（MOS器件）和闭锁（CMOS器件）的实质性抗扰性。

17. 发明授权

US4471524A Method for manufacturing an insulated gate field effect transistor device 失效
标题翻译：绝缘栅场效应晶体管器件的制造方法
公开(公告)号：US4471524A
公开(公告)日：1984-09-18
申请号：US564368
申请日：1983-12-23
申请人： Eliezer Kinsbron , William T. Lynch
发明人： Eliezer Kinsbron , William T. Lynch
IPC分类号： H01L21/225 , H01L21/28
CPC分类号： H01L21/225 , H01L21/28 , Y10S438/92
摘要： An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.
摘要翻译：公开了一种用于制造具有极浅源极和漏极区域以及减小的栅极至源极和漏极重叠电容的IGFET器件的总体方法。对于硅MOS器件，该方法还提供了在同一制造步骤中在多晶硅栅极电极和互连路径以及源极和漏极区域上形成金属硅化物层的方法。源极和漏极区域通过形成为与要形成这些区域的硅表面中的区域形成的砷掺杂多晶硅源层的氧化形成。源层的氧化速率超过在氧化温度下砷扩散的速率。由于二氧化硅中砷的分离系数高，源层中几乎所有的砷都被驱动到获得高表面浓度的极浅的源极和漏极区域。

18. 发明授权

US5630905A Method of fabricating quantum bridges by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造量子桥的方法
公开(公告)号：US5630905A
公开(公告)日：1997-05-20
申请号：US465493
申请日：1995-06-05
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L21/20
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

19. 发明授权

US5449642A Method of forming metal-disilicide layers and contacts 失效
标题翻译：形成金属二硅化物层和接触的方法
公开(公告)号：US5449642A
公开(公告)日：1995-09-12
申请号：US227659
申请日：1994-04-14
申请人： Teh Y. Tan , Gary E. McGuire , William T. Lynch
发明人： Teh Y. Tan , Gary E. McGuire , William T. Lynch
IPC分类号： H01L21/285 , H01L21/336 , H01L23/482 , H01L29/45 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66772 , H01L21/28518 , H01L23/4825 , H01L29/458 , H01L2924/0002
摘要： A method of forming a metal-disilicide (MSi.sub.2) film from a silicon-on-insulator (SOI) substrate having an insulating underlayer and a silicon outerlayer includes the formation of a first capping layer on a portion of the silicon outerlayer. The first capping layer preferably includes titanium and a preselected metal (M) such as cobalt. A step is then performed to convert a first portion of the silicon outerlayer to metal-disilicide. This step is preferably accomplished by a rapid thermal annealing step. Thereafter, a second capping layer is formed on the metal-disilicide layer. The second capping layer preferably includes titanium and metal-monosilicide (MSi). Next, a step is performed to convert a second portion of the silicon outerlayer, beneath the first portion, to metal-disilicide while preventing phase-reversal of the already formed metal-disilicide layer to metal-monosilicide. This step is preferably accomplished by a rapid thermal annealing step as well. The method can preferably be used to form low resistance metal-disilicide contacts to active regions of SOI electronic devices.
摘要翻译：从具有绝缘底层和硅外层的绝缘体上硅（SOI）衬底形成金属二硅化物（MSi2）膜的方法包括在硅外层的一部分上形成第一覆盖层。第一覆盖层优选包括钛和预选的金属（M）如钴。然后进行步骤以将硅外层的第一部分转化为金属二硅化物。该步骤优选通过快速热退火步骤完成。此后，在金属二硅化物层上形成第二覆盖层。第二盖层优选包括钛和金属一硅化物（MSi）。接下来，执行步骤，以将第二部分之下的硅外层的第二部分在第一部分之下转化为金属二硅化物，同时防止已经形成的金属二硅化物层与金属一硅化物相反相。该步骤也优选通过快速热退火步骤完成。该方法可优选用于形成低电阻金属二硅化物与SOI电子器件的有源区的接触。

20. 发明授权

US4914502A Laterally marching interconnecting lines in semiconductor intergrated circuits 失效
标题翻译：半导体集成电路中的纵向行进互连线路
公开(公告)号：US4914502A
公开(公告)日：1990-04-03
申请号：US147038
申请日：1988-01-29
申请人： Joseph Lebowitz , William T. Lynch
发明人： Joseph Lebowitz , William T. Lynch
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/108
CPC分类号： H01L23/528 , H01L23/5222 , H01L2924/0002
摘要： In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example, an array of word lines, of bit lines, or of bus interconnects--are geometrically arranged in a systematically progressive laterally (sidewise) marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.
摘要翻译：为了减少集成电路中的寄生电容交叉耦合，阵列中的金属化线（例如字线阵列，位线阵列或总线互连）几何地布置在系统地进行的侧向（侧向）行进序列，从而位于给定行的任一侧的线的身份不断变化。

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