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11. 发明授权

US08782346B2 Dynamic prioritization of cache access 失效
标题翻译：高速缓存访问的动态优先级
公开(公告)号：US08782346B2
公开(公告)日：2014-07-15
申请号：US13586518
申请日：2012-08-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold.
摘要翻译：本发明的一些实施例涉及确定存储器访问请求导致高速缓存未命中，并且响应于确定存储器访问请求导致高速缓存而确定用于在过去时段内服务高速缓存未命中的高速缓存资源量小姐。一些实施例进一步涉及确定对存储器访问请求的服务将增加用于在过去时间段内服务高速缓存未命中的高速缓存资源的数量超过阈值。在一些实施例中，阈值对应于用于潜在高速缓存命中的给定量的高速缓存资源的预留。响应于确定对存储器访问请求的服务会增加在过去时间段内用于服务高速缓存未命中的高速缓存资源的数量超过阈值，一些实施例进一步涉及拒绝存储器访问请求。

12. 发明申请

US20130151788A1 DYNAMIC PRIORITIZATION OF CACHE ACCESS 有权
标题翻译：缓存访问动态优先
公开(公告)号：US20130151788A1
公开(公告)日：2013-06-13
申请号：US13323076
申请日：2011-12-12
申请人： Robert H. Bell, JR. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.
摘要翻译：本发明主题的一些实施例涉及包括跟踪单元和高速缓存状态机的高速缓存。在一些实施例中，跟踪单元被配置为跟踪用于在过去时间段内服务高速缓存未命中的高速缓存资源的量。在一些实施例中，每个高速缓存状态机被配置为，确定存储器访问请求是否导致高速缓存未命中或高速缓存命中，并且响应于存储器访问请求的高速缓存未命中，查询跟踪单元的数量用于在过去一段时间内缓存未命中服务的缓存资源。在一些实施例中，每个高速缓存状态机被配置为至少部分地基于用于根据跟踪单元在过去时段内服务高速缓存未命中的高速缓存资源的量来服务存储器访问请求。

13. 发明申请

US20130111136A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111136A1
公开(公告)日：2013-05-02
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

14. 发明申请

US20120180052A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 失效
标题翻译：支持应用程序性能，支持在硬件中重新启动未经确认的软件启动的线程
公开(公告)号：US20120180052A1
公开(公告)日：2012-07-12
申请号：US13427045
申请日：2012-03-22
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/455
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
摘要翻译：公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核心的预取引擎可用性。如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

15. 发明申请

US20120096241A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 有权
公开(公告)号：US20120096241A1
公开(公告)日：2012-04-19
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

16. 发明授权

US09323527B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
标题翻译：使用瞬态指令流在虚拟化环境中的新兴应用程序的性能
公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

17. 发明申请

US20080165800A1 METHOD AND APPARATUS TO PROVIDE DYNAMIC COST OF CONTEXT SWITCH TO APPLICATION FOR PERFORMANCE OPTIMIZATION 审中-公开
标题翻译：提供上下文开关动态成本的方法和装置，以应用于性能优化
公开(公告)号：US20080165800A1
公开(公告)日：2008-07-10
申请号：US11621215
申请日：2007-01-09
申请人： Wen-Tzer T. Chen , Men-Chow Chiang , William A. Maron , Mysore S. Srinivas
发明人： Wen-Tzer T. Chen , Men-Chow Chiang , William A. Maron , Mysore S. Srinivas
IPC分类号： H04J3/22
CPC分类号： G06F9/526
摘要： A mechanism is provided in the operating system for recording context switch times. The operating system, the application, or the resource also includes a mechanism for recording response times. At the time of a request, the operating system may compare an average context switch time to an average response time corresponding to the request. The operating system may then decide whether to perform a context switch based on the comparison. Alternatively, the application may receive the average context switch time from the operating system and compare the average context switch time to an average response time corresponding to the request. The application may then decide whether to relinquish the processor or spin on the lock based on the comparison.
摘要翻译：在操作系统中提供用于记录上下文切换时间的机制。操作系统，应用程序或资源还包括用于记录响应时间的机制。在请求时，操作系统可以将平均上下文切换时间与对应于请求的平均响应时间进行比较。然后，操作系统可以基于比较来决定是否执行上下文切换。或者，应用可以从操作系统接收平均上下文切换时间，并将平均上下文切换时间与对应于请求的平均响应时间进行比较。然后，应用程序可以基于比较来决定是否放弃处理器或旋转锁定。

18. 发明授权

US06845504B2 Method and system for managing lock contention in a computer system 有权
标题翻译：在计算机系统中管理锁争用的方法和系统
公开(公告)号：US06845504B2
公开(公告)日：2005-01-18
申请号：US09779369
申请日：2001-02-08
申请人： Hong L. Hua , Bret R. Olszewski , Mysore S. Srinivas , Nasr-Eddine Walehiane
发明人： Hong L. Hua , Bret R. Olszewski , Mysore S. Srinivas , Nasr-Eddine Walehiane
IPC分类号： G06F7/00 , G06F9/46 , G06F12/00
CPC分类号： G06F9/526
摘要： A system and method for efficiently managing lock contention for a central processing unit (CPU) of a computer system. The present invention uses both spinning and blocking (or undispatching) to manage threads when they are waiting to acquire a lock. In addition, the present invention intelligently determines when the program thread should spin and when the program thread should become undispatched. If it is determined that the program thread should become undispatched, the present invention provides efficient undispatching of program threads that improves throughput by reducing wait time to acquire the lock. A lock contention management system includes a dispatcher for managing the execution of threads on CPUs as well as threads that are currently ready to run but not executing because they are waiting for an available CPU, a dispatch management module that determines when a program thread should become undispatched to wait on a lock and when the program thread should spin, and low-priority execution module for undispatching the program thread. The present invention also includes a lock contention management method using the above system.
摘要翻译：一种用于有效地管理计算机系统的中央处理单元（CPU）的锁争用的系统和方法。本发明使用旋转和阻塞（或未分配）来管理线程在等待获取锁定时。此外，本发明智能地确定程序线程何时旋转以及程序线程何时变为未分配。如果确定程序线程应该不分配，则本发明提供了通过减少获取锁定的等待时间来提高吞吐量的程序线程的有效的未分配。锁争用管理系统包括调度器，用于管理CPU上的线程的执行以及当前准备运行但未执行的线程，因为它们正在等待可用的CPU，调度管理模块确定程序线程何时应该成为未分配等待锁和程序线程应该旋转，而低优先级的执行模块用于对程序线程进行分配。本发明还包括使用上述系统的锁争用管理方法。

19. 发明授权

US08695011B2 Mixed operating performance modes including a shared cache mode 有权
公开(公告)号：US08695011B2
公开(公告)日：2014-04-08
申请号：US13458769
申请日：2012-04-27
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F1/00 , G06F13/00
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

20. 发明授权

US08539281B2 Managing rollback in a transactional memory environment 有权
标题翻译：在事务性内存环境中管理回滚
公开(公告)号：US08539281B2
公开(公告)日：2013-09-17
申请号：US13451266
申请日：2012-04-19
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F11/00
CPC分类号： G06F9/528 , G06F9/467
摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对第二个内存位置，并指示需要回滚。该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

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