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1. 发明授权

US09065840B2 Determining server write activity levels to use to adjust write cache size 有权
标题翻译：确定用于调整写缓存大小的服务器写入活动级别
公开(公告)号：US09065840B2
公开(公告)日：2015-06-23
申请号：US13478868
申请日：2012-05-23
申请人： Robert H. Bell, Jr. , Michael D. Roll , Olga Yiparaki
发明人： Robert H. Bell, Jr. , Michael D. Roll , Olga Yiparaki
IPC分类号： G06F12/00 , H04L29/08 , G06F11/34
CPC分类号： H04L67/1097 , G06F11/3409 , G06F11/3442 , G06F11/3485 , G06F2201/81 , G06F2201/88 , G06F2201/885 , H04L67/2847 , H04L67/2852 , H04L67/34 , Y02D10/34
摘要： Provided are a computer program product, system, and method for determining server write activity levels to use to adjust write cache size. Information on server write activity to the cache is gathered. The gathered information on write activity is processed to determine a server write activity level comprising one of multiple write activity levels indicating a level of write activity. The determined server write activity level is transmitted to a storage server having a write cache, wherein the storage server uses the determined server write activity level to determine whether to adjust a size of the storage server write cache.
摘要翻译：提供了一种用于确定用于调整写入高速缓存大小的服务器写入活动级别的计算机程序产品，系统和方法。收集有关缓存服务器写入活动的信息。处理收集的关于写入活动的信息以确定包括指示写入活动级别的多个写入活动级别中的一个的服务器写入活动级别。确定的服务器写入活动级别被发送到具有写入高速缓存的存储服务器，其中存储服务器使用所确定的服务器写入活动级别来确定是否调整存储服务器写入高速缓存的大小。

2. 发明授权

US08886918B2 Dynamic instruction execution based on transaction priority tagging 有权
标题翻译：基于事务优先级标记的动态指令执行
公开(公告)号：US08886918B2
公开(公告)日：2014-11-11
申请号：US11946504
申请日：2007-11-28
申请人： Louis B. Capps, Jr. , Robert H. Bell, Jr.
发明人： Louis B. Capps, Jr. , Robert H. Bell, Jr.
IPC分类号： G06F9/30 , G06F11/34 , G06F9/50 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/3851 , G06F9/5011 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/885 , G06F2209/507 , Y02D10/22 , Y02D10/34
摘要： A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies. The test results may be used to optimize the workload allocation of system resources by dynamically assigning thread priority values to individual threads using any desired policy, such as achieving thread execution balance relative to thresholds and to performance of other threads, reducing thread response time, lowering power consumption, etc.
摘要翻译：提供了一种方法，系统和程序，用于基于一个或多个预定的线程性能测试来动态地为计算机系统中的指令线程分配优先级值，并且使用所分配的指令优先级来确定如何在系统中使用资源。通过将每个线程的分配优先级值作为标签存储在线程的指令中，基于分配给各个指令线程的标记的优先级值来分配来自系统调度的来自不同线程的标记指令。可以使用测试线程性能的控制软件更新各个线程的优先级值，并使用测试结果来应用预定的调整策略。测试结果可用于通过使用任何期望的策略动态地将线程优先级值分配给各个线程来优化系统资源的工作量分配，例如实现相对于阈值的线程执行平衡以及其他线程的性能，减少线程响应时间，降低功耗等

3. 发明授权

US08645673B2 Multicore processor and method of use that adapts core functions based on workload execution 失效
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08645673B2
公开(公告)日：2014-02-04
申请号：US13613936
申请日：2012-09-13
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/06 , G06F9/24
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

4. 发明授权

US08544006B2 Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict 有权
标题翻译：通过在发生冲突后由主要组件生成的寄存器和内存值重新启动失败的离散可执行子组件的执行来解决冲突
公开(公告)号：US08544006B2
公开(公告)日：2013-09-24
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

5. 发明授权

US08527997B2 Energy-aware job scheduling for cluster environments 失效
公开(公告)号：US08527997B2
公开(公告)日：2013-09-03
申请号：US13458860
申请日：2012-04-27
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
IPC分类号： G06F9/46 , G06F1/26
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A job scheduler can select a processor core operating frequency for a node in a cluster to perform a job based on energy usage and performance data. After a job request is received, an energy aware job scheduler accesses data that specifies energy usage and job performance metrics that correspond to the requested job and a plurality of processor core operating frequencies. A first of the plurality of processor core operating frequencies is selected that satisfies an energy usage criterion for performing the job based, at least in part, on the data that specifies energy usage and job performance metrics that correspond to the job. The job is assigned to be performed by a node in the cluster at the selected first of the plurality of processor core operating frequencies.

6. 发明授权

US08495342B2 Configuring plural cores to perform an instruction having a multi-core characteristic 有权
标题翻译：配置多个内核以执行具有多核特性的指令
公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

7. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

8. 发明申请

US20120221812A1 METHOD FOR PRESERVING MEMORY AFFINITY IN A NON-UNIFORM MEMORY ACCESS DATA PROCESSING SYSTEM 审中-公开
标题翻译：在非均匀存储器访问数据处理系统中保存存储器的方法
公开(公告)号：US20120221812A1
公开(公告)日：2012-08-30
申请号：US13455567
申请日：2012-04-25
申请人： MATHEW ACCAPADI , ROBERT H. BELL, JR. , MEN-CHOW CHIANG , HONG L. HUA
发明人： MATHEW ACCAPADI , ROBERT H. BELL, JR. , MEN-CHOW CHIANG , HONG L. HUA
IPC分类号： G06F12/00
CPC分类号： G06F9/5016 , G06F9/5088 , G06F2212/2542 , Y02D10/22 , Y02D10/32
摘要： A method for preserving memory affinity in a computer system is disclosed. The method reduces and sometimes eliminates memory affinity loss due to process migration by restoring the proper memory affinity through dynamic page migration. The memory affinity access patterns of individual pages are tracked continuously. If a particular page is found almost always to be accessed from a particular remote access affinity domain for a certain number of times, and without any intervening requests from other access affinity domain, the page will migrate to that particular remote affinity domain so that the subsequent memory access becomes local memory access. As a result, the proper pages are migrated to increase memory affinity.
摘要翻译：公开了一种在计算机系统中保存记忆亲和性的方法。该方法通过动态页面迁移恢复适当的内存亲和力，减少了有时消除了进程迁移造成的内存亲和力损失。各个页面的存储器亲和访问模式被连续跟踪。如果发现特定页面几乎总是从特定的远程访问关联域访问一定次数，并且没有来自其他访问关联域的任何中介请求，则页面将迁移到该特定远程关联域，以便后续内存访问成为本地内存访问。结果，适当的页面被迁移以增加记忆亲和力。

9. 发明授权

US07904870B2 Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering 有权
标题翻译：集成电路设计模型性能评估的方法和装置，采用基本的块矢量聚类和飞行矢量聚类
公开(公告)号：US07904870B2
公开(公告)日：2011-03-08
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

10. 发明授权

US07568076B2 Variable store gather window 有权
标题翻译：变量存储收集窗口
公开(公告)号：US07568076B2
公开(公告)日：2009-07-28
申请号：US11836872
申请日：2007-08-10
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

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