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1. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

2. 发明授权

US08935478B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08935478B2
公开(公告)日：2015-01-13
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

3. 发明申请

US20130111136A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111136A1
公开(公告)日：2013-05-02
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

4. 发明授权

US08943272B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08943272B2
公开(公告)日：2015-01-27
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

5. 发明授权

US08972706B2 Performance in predicting branches 有权
标题翻译：在预测分支中的表现
公开(公告)号：US08972706B2
公开(公告)日：2015-03-03
申请号：US13116515
申请日：2011-05-26
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.
摘要翻译：用于处理指令的数据处理系统和计算机程序产品。所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。形成与标记相符的指令的标识。识别由标记引用的多个表中的第二表。第二个表用于代替第一个表。

6. 发明授权

US08539281B2 Managing rollback in a transactional memory environment 有权
标题翻译：在事务性内存环境中管理回滚
公开(公告)号：US08539281B2
公开(公告)日：2013-09-17
申请号：US13451266
申请日：2012-04-19
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F11/00
CPC分类号： G06F9/528 , G06F9/467
摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对第二个内存位置，并指示需要回滚。该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

7. 发明申请

US20120124299A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXTENDING A CACHE USING PROCESSOR REGISTERS 失效
标题翻译：使用处理器寄存器扩展缓存的系统，方法和计算机程序产品
公开(公告)号：US20120124299A1
公开(公告)日：2012-05-17
申请号：US12945354
申请日：2010-11-12
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
摘要翻译：根据本公开的一个方面，公开了一种使用处理器寄存器来扩展高速缓存结构的方法和技术。该方法包括识别处理器的寄存器，识别要扩展的高速缓存，将该寄存器分配为高速缓存的扩展，以及将寄存器的地址设置为对应于高速缓存中的地址空间。

8. 发明授权

US08677050B2 System, method and computer program product for extending a cache using processor registers 失效
标题翻译：用于使用处理器寄存器扩展缓存的系统，方法和计算机程序产品
公开(公告)号：US08677050B2
公开(公告)日：2014-03-18
申请号：US12945354
申请日：2010-11-12
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/00
CPC分类号： G06F12/0895
摘要： According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
摘要翻译：根据本公开的一个方面，公开了一种使用处理器寄存器来扩展高速缓存结构的方法和技术。该方法包括识别处理器的寄存器，识别要扩展的高速缓存，将该寄存器分配为高速缓存的扩展，以及将寄存器的地址设置为对应于高速缓存中的地址空间。

9. 发明申请

US20120304002A1 MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT 有权
标题翻译：管理在一个交易记忆环境中的滚动
公开(公告)号：US20120304002A1
公开(公告)日：2012-11-29
申请号：US13113663
申请日：2011-05-23
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F11/07
CPC分类号： G06F9/528 , G06F9/467
摘要： A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：公开了一种用于在事务性存储器环境中管理回滚的系统和技术。该系统包括处理器，事务存储器和被配置为在事务存储器上执行回滚的事务性存储器管理器（TMM）。 TMM被配置为响应于检测到处理器的开始事务指令，检测不需要回滚的事务存储器的第一存储器位置的访问，并且指示在检测到访问期间不需要回滚第一存储器位置到事务存储器的第二存储器位置并且指示将需要回滚。 TMM还被配置为响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置处执行回滚时，省略第一存储器位置的回滚。

10. 发明申请

US20120303591A1 MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT 有权
标题翻译：管理在一个交易记忆环境中的滚动
公开(公告)号：US20120303591A1
公开(公告)日：2012-11-29
申请号：US13451266
申请日：2012-04-19
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F17/30
CPC分类号： G06F9/528 , G06F9/467
摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对第二个内存位置，并指示需要回滚。该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

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