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1. 发明授权

US09323527B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
标题翻译：使用瞬态指令流在虚拟化环境中的新兴应用程序的性能
公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

2. 发明申请

US20120096240A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 有权
公开(公告)号：US20120096240A1
公开(公告)日：2012-04-19
申请号：US12905176
申请日：2010-10-15
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/38 , G06F9/455 , G06F9/30
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

3. 发明申请

US20120180052A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 失效
标题翻译：支持应用程序性能，支持在硬件中重新启动未经确认的软件启动的线程
公开(公告)号：US20120180052A1
公开(公告)日：2012-07-12
申请号：US13427045
申请日：2012-03-22
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/455
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
摘要翻译：公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核心的预取引擎可用性。如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

4. 发明申请

US20120096241A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 有权
公开(公告)号：US20120096241A1
公开(公告)日：2012-04-19
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

5. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

6. 发明申请

US20120179873A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 审中-公开
标题翻译：使用瞬态指令流在虚拟化环境中新兴应用的性能
公开(公告)号：US20120179873A1
公开(公告)日：2012-07-12
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以写入L1和低级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

7. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

8. 发明授权

US08438334B2 Hybrid storage subsystem with mixed placement of file contents 有权
公开(公告)号：US08438334B2
公开(公告)日：2013-05-07
申请号：US12644721
申请日：2009-12-22
申请人： Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/30082 , G06F3/0611 , G06F3/064 , G06F3/0647 , G06F3/0685
摘要： A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.

9. 发明授权

US08935478B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08935478B2
公开(公告)日：2015-01-13
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

10. 发明授权

US08782346B2 Dynamic prioritization of cache access 失效
标题翻译：高速缓存访问的动态优先级
公开(公告)号：US08782346B2
公开(公告)日：2014-07-15
申请号：US13586518
申请日：2012-08-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold.
摘要翻译：本发明的一些实施例涉及确定存储器访问请求导致高速缓存未命中，并且响应于确定存储器访问请求导致高速缓存而确定用于在过去时段内服务高速缓存未命中的高速缓存资源量小姐。一些实施例进一步涉及确定对存储器访问请求的服务将增加用于在过去时间段内服务高速缓存未命中的高速缓存资源的数量超过阈值。在一些实施例中，阈值对应于用于潜在高速缓存命中的给定量的高速缓存资源的预留。响应于确定对存储器访问请求的服务会增加在过去时间段内用于服务高速缓存未命中的高速缓存资源的数量超过阈值，一些实施例进一步涉及拒绝存储器访问请求。

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