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1. 发明授权

US08677371B2 Mixed operating performance modes including a shared cache mode 有权
标题翻译：混合操作性能模式，包括共享缓存模式
公开(公告)号：US08677371B2
公开(公告)日：2014-03-18
申请号：US12650909
申请日：2009-12-31
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F1/00 , G06F13/00
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组关联。

2. 发明申请

US20120216214A1 MIXED OPERATING PERFORMANCE MODE LPAR CONFIGURATION 有权
标题翻译：混合操作性能模式LPAR配置
公开(公告)号：US20120216214A1
公开(公告)日：2012-08-23
申请号：US13458769
申请日：2012-04-27
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组相关联。

3. 发明授权

US08695011B2 Mixed operating performance modes including a shared cache mode 有权
公开(公告)号：US08695011B2
公开(公告)日：2014-04-08
申请号：US13458769
申请日：2012-04-27
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F1/00 , G06F13/00
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

4. 发明申请

US20110161979A1 MIXED OPERATING PERFORMANCE MODE LPAR CONFIGURATION 有权
标题翻译：混合操作性能模式LPAR配置
公开(公告)号：US20110161979A1
公开(公告)日：2011-06-30
申请号：US12650909
申请日：2009-12-31
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组相关联。

5. 发明授权

US08972706B2 Performance in predicting branches 有权
标题翻译：在预测分支中的表现
公开(公告)号：US08972706B2
公开(公告)日：2015-03-03
申请号：US13116515
申请日：2011-05-26
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.
摘要翻译：用于处理指令的数据处理系统和计算机程序产品。所述指令由处理器单元处理，同时使用多个表中的第一表来预测在处理条件指令之后所述处理器单元所需的一组指令。形成识别，即当使用第一表时正确预测指令集的成功率小于阈值数。搜索由处理器单元处理的指令的序列，以搜索与用于识别何时使用多个表的一组标记中的标记相匹配的指令。形成与标记相符的指令的标识。识别由标记引用的多个表中的第二表。第二个表用于代替第一个表。

6. 发明申请

US20130111135A1 VARIABLE CACHE LINE SIZE MANAGEMENT 有权
标题翻译：可变缓存线尺寸管理
公开(公告)号：US20130111135A1
公开(公告)日：2013-05-02
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

7. 发明授权

US08539281B2 Managing rollback in a transactional memory environment 有权
标题翻译：在事务性内存环境中管理回滚
公开(公告)号：US08539281B2
公开(公告)日：2013-09-17
申请号：US13451266
申请日：2012-04-19
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F11/00
CPC分类号： G06F9/528 , G06F9/467
摘要： According to one aspect of the present disclosure, a method and technique for managing rollback in a transactional memory environment is disclosed. The method includes, responsive to detecting a begin transaction directive by a processor supporting transactional memory processing, detecting an access of a first memory location not needing rollback and indicating that the first memory location does not need to be rolled back while detecting an access to a second memory location and indicating that a rollback will be required. The method also includes, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omitting a rollback of the first memory location while performing rollback on the second memory location.
摘要翻译：根据本公开的一个方面，公开了一种用于在事务存储器环境中管理回滚的方法和技术。该方法包括：响应于由支持事务性存储器处理的处理器检测开始事务指令，检测不需要回滚的第一存储器位置的访问，并指示第一存储器位置不需要回滚，同时检测到对第二个内存位置，并指示需要回滚。该方法还包括：响应于在开始事务指令之后检测到结束事务指令和需要回滚的冲突，在第二存储器位置上执行回滚的同时省略第一存储器位置的回滚。

8. 发明授权

US08301840B2 Assigning cache priorities to virtual/logical processors and partitioning a cache according to such priorities 失效
标题翻译：将缓存优先级分配给虚拟/逻辑处理器，并根据这些优先级对高速缓存进行分区
公开(公告)号：US08301840B2
公开(公告)日：2012-10-30
申请号：US12637891
申请日：2009-12-15
申请人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
发明人： Vaijayanthimala K. Anand , Diane G. Flemming , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/12
CPC分类号： G06F12/0895 , G06F9/5022 , G06F9/5077 , G06F12/126 , G06F2209/5021
摘要： Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.
摘要翻译：提供了用于在具有至少一个物理处理器和至少一个相关联的高速缓冲存储器的数据处理系统中实现的机制，用于将至少一个高速缓冲存储器的高速缓存资源分配给数据处理系统的虚拟处理器。该机制识别数据处理系统中的多个高优先级虚拟处理器。这些机制进一步确定要分配给高优先级虚拟处理器的至少一个高速缓冲存储器的高速缓存行的百分比。此外，机制将所述至少一个高速缓冲存储器中的高速缓存行的一部分标记为仅基于所分配给高优先级虚拟处理器的高速缓存行的确定百分比仅被高优先级的虚拟处理器驱逐。高速缓存行的标记部分不能被优先级低于高优先级虚拟处理器的较低优先级的虚拟处理器驱逐。

9. 发明申请

US20120124299A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXTENDING A CACHE USING PROCESSOR REGISTERS 失效
标题翻译：使用处理器寄存器扩展缓存的系统，方法和计算机程序产品
公开(公告)号：US20120124299A1
公开(公告)日：2012-05-17
申请号：US12945354
申请日：2010-11-12
申请人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
发明人： Wen-Tzer T. Chen , Diane G. Flemming , William A. Maron , Mysore S. Srinivas , David B. Whitworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.
摘要翻译：根据本公开的一个方面，公开了一种使用处理器寄存器来扩展高速缓存结构的方法和技术。该方法包括识别处理器的寄存器，识别要扩展的高速缓存，将该寄存器分配为高速缓存的扩展，以及将寄存器的地址设置为对应于高速缓存中的地址空间。

10. 发明授权

US08935478B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08935478B2
公开(公告)日：2015-01-13
申请号：US13286507
申请日：2011-11-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的系统和技术。该系统包括处理器和高速缓存层级，其中高速缓存分层结构包括扇区高级缓存和未被覆盖的较低级高速缓存，并且其中高级高速缓存包括多个子扇区，每个子扇区具有高速缓存行大小对应于较低级别缓存的高速缓存行大小。该系统还包括可执行的逻辑，用于响应于确定来自较高级别高速缓存的高速缓存线将被驱逐到较低级高速缓存：识别要驱逐的高速缓存行的参考子扇区; 使缓存行的未引用子扇区无效; 并将参考的子扇区存储在较低级别的高速缓存中。

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