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1. 发明授权

US09323527B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
标题翻译：使用瞬态指令流在虚拟化环境中的新兴应用程序的性能
公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

2. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

3. 发明申请

US20120179873A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 审中-公开
标题翻译：使用瞬态指令流在虚拟化环境中新兴应用的性能
公开(公告)号：US20120179873A1
公开(公告)日：2012-07-12
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以写入L1和低级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

4. 发明申请

US20120096240A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 有权
公开(公告)号：US20120096240A1
公开(公告)日：2012-04-19
申请号：US12905176
申请日：2010-10-15
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/38 , G06F9/455 , G06F9/30
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

5. 发明申请

US20120180052A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 失效
标题翻译：支持应用程序性能，支持在硬件中重新启动未经确认的软件启动的线程
公开(公告)号：US20120180052A1
公开(公告)日：2012-07-12
申请号：US13427045
申请日：2012-03-22
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/455
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
摘要翻译：公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核心的预取引擎可用性。如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

6. 发明申请

US20120096241A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 有权
公开(公告)号：US20120096241A1
公开(公告)日：2012-04-19
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

7. 发明申请

US20110161979A1 MIXED OPERATING PERFORMANCE MODE LPAR CONFIGURATION 有权
标题翻译：混合操作性能模式LPAR配置
公开(公告)号：US20110161979A1
公开(公告)日：2011-06-30
申请号：US12650909
申请日：2009-12-31
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组相关联。

8. 发明授权

US08695011B2 Mixed operating performance modes including a shared cache mode 有权
公开(公告)号：US08695011B2
公开(公告)日：2014-04-08
申请号：US13458769
申请日：2012-04-27
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F1/00 , G06F13/00
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.

9. 发明授权

US08677371B2 Mixed operating performance modes including a shared cache mode 有权
标题翻译：混合操作性能模式，包括共享缓存模式
公开(公告)号：US08677371B2
公开(公告)日：2014-03-18
申请号：US12650909
申请日：2009-12-31
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F1/00 , G06F13/00
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组关联。

10. 发明申请

US20120216214A1 MIXED OPERATING PERFORMANCE MODE LPAR CONFIGURATION 有权
标题翻译：混合操作性能模式LPAR配置
公开(公告)号：US20120216214A1
公开(公告)日：2012-08-23
申请号：US13458769
申请日：2012-04-27
申请人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
发明人： Diane G. Flemming , William A. Maron , Ram Raghavan , Satya Prakash Sharma , Mysore S. Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： Functionality is implemented to determine that a plurality of multi-core processing units of a system are configured in accordance with a plurality of operating performance modes. It is determined that a first of the plurality of operating performance modes satisfies a first performance criterion that corresponds to a first workload of a first logical partition of the system. Accordingly, the first logical partition is associated with a first set of the plurality of multi-core processing units that are configured in accordance with the first operating performance mode. It is determined that a second of the plurality of operating performance modes satisfies a second performance criterion that corresponds to a second workload of a second logical partition of the system. Accordingly, the second logical partition is associated with a second set of the plurality of multi-core processing units that are configured in accordance with the second operating performance mode.
摘要翻译：实现功能以确定系统的多个多核处理单元根据多个操作性能模式来配置。确定多个操作性能模式中的第一个满足与系统的第一逻辑分区的第一工作负载相对应的第一性能标准。因此，第一逻辑分区与根据第一操作性能模式配置的多个多核处理单元的第一组相关联。确定多个操作性能模式中的第二个满足与系统的第二逻辑分区的第二工作负载相对应的第二性能标准。因此，第二逻辑分区与根据第二操作性能模式配置的多个多核处理单元的第二组相关联。

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