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11. 发明申请

US20090327548A1 Scalable Bus Structure 审中-公开
标题翻译：可扩展总线结构
公开(公告)号：US20090327548A1
公开(公告)日：2009-12-31
申请号：US12551590
申请日：2009-09-01
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： G06F13/4265
摘要： A method of communicating over a bus is disclosed and includes transmitting a first data type in a first type field over a first sub-channel of a transmit channel of the bus while concurrently transmitting a second data type in a second type field over a second sub-channel of the transmit channel of the bus. The method also includes receiving data over a receive channel of the bus while transmitting the first data type and the second data type over the transmit channel.
摘要翻译：公开了一种通过总线进行通信的方法，包括在总线的发送信道的第一子信道上在第一类型字段中发送第一数据类型，同时在第二子字段中在第二类型字段中发送第二数据类型 - 总线的发送通道的通道。该方法还包括在通过发送信道发送第一数据类型和第二数据类型的同时在总线的接收信道上接收数据。

12. 发明授权

US07395361B2 Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth 有权
标题翻译：基于传输方向和/或消耗带宽，在多个主设备之间进行加权总线仲裁的装置和方法
公开(公告)号：US07395361B2
公开(公告)日：2008-07-01
申请号：US11208089
申请日：2005-08-19
申请人： Mark Michael Schaffer , Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan
发明人： Mark Michael Schaffer , Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.
摘要翻译：总线仲裁算法通过考虑总线事务消耗的方向和/或总线信道带宽来精确地控制分配给每个主设备的相对总线信道带宽。至少一个加权寄存器与每个主设备相关联; 在一个实施例中，每个总线信道有一个加权寄存器。寄存器定期加载可用总线带宽的比例份额。在总线信道被授予总线事务后，对应的加权寄存器减少反映交易消耗的总线信道带宽的量，以传输的数据量或完成交易所需的总线数据传送周期的数量进行测量。在初始分配相对带宽份额相同的情况下，消耗总线信道带宽的主设备优先级相对较低; 不消耗总线信道带宽的主设备保持较高的优先级。

13. 发明授权

US07185123B2 Method and apparatus for allocating bandwidth on a transmit channel of a bus 有权
标题翻译：在总线的发送信道上分配带宽的方法和装置
公开(公告)号：US07185123B2
公开(公告)日：2007-02-27
申请号：US10942291
申请日：2004-09-15
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/00
CPC分类号： G06F13/24
摘要： A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and resume the broadcast of the payload over the transmit channel. The processing system may include an algorithm that prevents small payloads from being interrupted to initiate a new bus operation. The algorithm may also be used to limit the number of times a single write operation may be interrupted to initiate a new bus operation.
摘要翻译：公开了一种在处理系统内通信的处理系统和方法。处理系统可以包括具有发射信道的总线，接收组件和被配置为通过发射信道广播有效载荷到接收组件的发送组件，中断有效载荷的广播以向接收组件发出新的总线操作并通过发送信道恢复有效载荷的广播。处理系统可以包括防止小负载被中断以启动新的总线操作的算法。该算法还可以用于限制单个写入操作可能被中断以启动新的总线操作的次数。

14. 发明授权

US06055584A Processor local bus posted DMA FlyBy burst transfers 失效
标题翻译：处理器本地总线发送DMA FlyBy突发传输
公开(公告)号：US06055584A
公开(公告)日：2000-04-25
申请号：US975540
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
摘要翻译：提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。从总线控制器还耦合到存储器单元。存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

15. 发明授权

US6052745A System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers 失效
标题翻译：用于在固定长度突发传输中在上一周期之前和之后一个周期断言突发终止信号和突发完整信号的系统
公开(公告)号：US6052745A
公开(公告)日：2000-04-18
申请号：US96943
申请日：1998-06-12
申请人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
发明人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and is optional so a master and slave who use the protocol of the present invention is compatible with masters and slaves who do not.
摘要翻译：本发明提供了一种在数据处理系统内的总线上的数据的固定长度突发的方法和系统。根据本发明的方法和系统提供突发传输协议，其包括当至少一个主设备从至少一个主设备到至少一个从设备的信号时提供固定长度的数据突发数据长度信息设备请求固定长度的数据突发。它还包括在固定长度脉冲串中的最后一个周期之前一个周期由至少一个从设备断言突发终止信号，以及在固定长度脉冲串中的最后一个周期期间断言突发完成信号以进行写入基于信号的值，在针对读取脉冲串的固定长度脉冲串中的最后一个周期之前的一个周期。该突发传输协议允许在主机和从机之间的本地总线上执行最大长度的突发传输，而在传输之后不会造成死循环损坏。这样可以提高局部总线上数据吞吐量的效率和性能，而无需增加频率。本发明不需要新的信号并且是可选的，所以使用本发明的协议的主设备和从设备与没有的主设备和从设备兼容。

16. 发明授权

US5926831A Methods and apparatus for control of speculative memory accesses 失效
标题翻译：用于控制存储器访问的方法和装置
公开(公告)号：US5926831A
公开(公告)日：1999-07-20
申请号：US731350
申请日：1996-10-11
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0215
摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.
摘要翻译：一种动态配置的存储器控制器，用于防止对非良好行为内存的推测性内存访问。可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

17. 发明授权

US08861410B2 Method and apparatus for scalable network transaction identifier for interconnects 有权
标题翻译：用于互连的可伸缩网络事务标识符的方法和装置
公开(公告)号：US08861410B2
公开(公告)日：2014-10-14
申请号：US13285215
申请日：2011-10-31
申请人： Jaya Prakash Subramaniam Ganasan , Prudhvi N. Nooney , Darren P. Umstead , Joseph L. Van Swearingen , Barry Joe Wolford , Mark Michael Schaffer
发明人： Jaya Prakash Subramaniam Ganasan , Prudhvi N. Nooney , Darren P. Umstead , Joseph L. Van Swearingen , Barry Joe Wolford , Mark Michael Schaffer
IPC分类号： H04B7/00
CPC分类号： H04L45/74
摘要： A transaction request passes from an initiator through interconnect paths and a routing ID indicating the interconnect paths is prepended. A temporary ID is assigned to the routing ID, the transaction request with the temporary ID is sent to a target device, and a response having the temporary ID is received. The routing ID is retrieved using the target ID, and the response with the retrieved routing ID is sent to the initiator.
摘要翻译：交易请求从发起者通过互连路径传递，并且指示互连路径的路由ID被添加。临时ID被分配给路由ID，具有临时ID的事务请求被发送到目标设备，并且接收到具有临时ID的响应。使用目标ID检索路由ID，并将具有检索到的路由ID的响应发送到启动器。

18. 发明授权

US08838861B2 Methods and apparatuses for trace multicast across a bus structure, and related systems 有权
标题翻译：通过总线结构跟踪组播的方法和装置，以及相关系统
公开(公告)号：US08838861B2
公开(公告)日：2014-09-16
申请号：US13531863
申请日：2012-06-25
申请人： Martyn Ryan Shirlen , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Mark Michael Schaffer
IPC分类号： G06F11/36
CPC分类号： G06F11/3656 , G06F11/364 , G06F13/4022
摘要： Systems and methods for trace multicast across a bus structure are provided. Preferably, the bus structure is that of a System-on-a-Chip (SoC), where the SoC includes a number of master components and a number of slave components connected via the bus structure. The bus structure supports a trace multicast feature. In one embodiment, the bus structure receives a bus transaction from a master component and, in response, outputs the bus transaction to a corresponding slave port. In addition, the bus structure determines whether a trace multicast is desired for the bus transaction. If a trace multicast is desired, the bus structure generates an additional bus transaction having one or more transaction attributes that include a translated version of the bus transaction and outputs the additional bus transaction to a trace slave port of the bus structure. The trace multicast feature provides a non-invasive mechanism for driver-level trace.
摘要翻译：提供了通过总线结构跟踪组播的系统和方法。优选地，总线结构是片上系统（SoC）的结构，其中SoC包括多个主组件和通过总线结构连接的多个从组件。总线结构支持跟踪组播功能。在一个实施例中，总线结构从主组件接收总线事务，并且作为响应，将总线事务输出到对应的从端口。此外，总线结构确定对于总线事务是否需要跟踪多播。如果需要跟踪多播，则总线结构生成具有一个或多个事务属性的附加总线事务，该事务属性包括总线事务的转换版本，并将附加总线事务输出到总线结构的跟踪从站端口。跟踪多播功能为驱动程序级跟踪提供了非侵入性机制。

19. 发明申请

US20130304955A1 Methods and Apparatuses for Trace Multicast Across a Bus Structure, and Related Systems 有权
标题翻译：通过总线结构跟踪组播的方法和设备及相关系统
公开(公告)号：US20130304955A1
公开(公告)日：2013-11-14
申请号：US13531863
申请日：2012-06-25
申请人： Martyn Ryan Shirlen , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Mark Michael Schaffer
IPC分类号： G06F13/20
CPC分类号： G06F11/3656 , G06F11/364 , G06F13/4022
摘要： Systems and methods for trace multicast across a bus structure are provided. Preferably, the bus structure is that of a System-on-a-Chip (SoC), where the SoC includes a number of master components and a number of slave components connected via the bus structure. The bus structure supports a trace multicast feature. In one embodiment, the bus structure receives a bus transaction from a master component and, in response, outputs the bus transaction to a corresponding slave port. In addition, the bus structure determines whether a trace multicast is desired for the bus transaction. If a trace multicast is desired, the bus structure generates an additional bus transaction having one or more transaction attributes that include a translated version of the bus transaction and outputs the additional bus transaction to a trace slave port of the bus structure. The trace multicast feature provides a non-invasive mechanism for driver-level trace.
摘要翻译：提供了通过总线结构跟踪组播的系统和方法。优选地，总线结构是片上系统（SoC）的结构，其中SoC包括多个主组件和通过总线结构连接的多个从组件。总线结构支持跟踪组播功能。在一个实施例中，总线结构从主组件接收总线事务，并且作为响应，将总线事务输出到对应的从端口。此外，总线结构确定对于总线事务是否需要跟踪多播。如果需要跟踪多播，则总线结构生成具有一个或多个事务属性的附加总线事务，该事务属性包括总线事务的转换版本，并将附加总线事务输出到总线结构的跟踪从站端口。跟踪多播功能为驱动程序级跟踪提供了非侵入性机制。

20. 发明授权

US5925118A Methods and architectures for overlapped read and write operations 失效
标题翻译：用于重叠读写操作的方法和体系结构
公开(公告)号：US5925118A
公开(公告)日：1999-07-20
申请号：US729555
申请日：1996-10-11
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/364 , G06F13/14
CPC分类号： G06F13/364
摘要： A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions. In a preferred embodiment of the present invention, the master function and the slave function are further connected by a plurality of transfer qualifier signals which may specify whether the operation is a read or a write operation, the size of the transfer, the direction of the transfer or the type of transfer so as to further facilitate multiple cycle transfers with a single address specified on the single address bus.
摘要翻译：通信系统和通信方法，其包括通过单个地址总线，写数据总线和读数据总线连接到主功能的从功能，以便允许在主功能和从机之间重叠多周期读和写操作功能。优选地，通信系统包括通过单个地址总线，写数据总线和读数据总线连接到主功能的多个从功能。多个主功能可以通过总线仲裁器连接到从属功能，总线仲裁器通过地址总线，写数据总线和用于每个主功能的读数据总线连接到多个主功能。总线仲裁器从多个主功能接收通信操作的请求，并且选择性地将通信操作发送到从属功能。在本发明的优选实施例中，主功能和从功能还通过多个传输限定符信号进一步连接，传输限定符可以指定操作是读还是写操作，传输的大小，传输的方向传输或传输类型，以便通过在单个地址总线上指定的单个地址来进一步促进多个周期传输。

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