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1. 发明授权

US6052745A System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers 失效
标题翻译：用于在固定长度突发传输中在上一周期之前和之后一个周期断言突发终止信号和突发完整信号的系统
公开(公告)号：US6052745A
公开(公告)日：2000-04-18
申请号：US96943
申请日：1998-06-12
申请人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
发明人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and is optional so a master and slave who use the protocol of the present invention is compatible with masters and slaves who do not.
摘要翻译：本发明提供了一种在数据处理系统内的总线上的数据的固定长度突发的方法和系统。根据本发明的方法和系统提供突发传输协议，其包括当至少一个主设备从至少一个主设备到至少一个从设备的信号时提供固定长度的数据突发数据长度信息设备请求固定长度的数据突发。它还包括在固定长度脉冲串中的最后一个周期之前一个周期由至少一个从设备断言突发终止信号，以及在固定长度脉冲串中的最后一个周期期间断言突发完成信号以进行写入基于信号的值，在针对读取脉冲串的固定长度脉冲串中的最后一个周期之前的一个周期。该突发传输协议允许在主机和从机之间的本地总线上执行最大长度的突发传输，而在传输之后不会造成死循环损坏。这样可以提高局部总线上数据吞吐量的效率和性能，而无需增加频率。本发明不需要新的信号并且是可选的，所以使用本发明的协议的主设备和从设备与没有的主设备和从设备兼容。

2. 发明授权

US07764084B2 Apparatus for reducing power consumption with configurable latches and registers 失效
标题翻译：可配置锁存器和寄存器降低功耗的设备
公开(公告)号：US07764084B2
公开(公告)日：2010-07-27
申请号：US12348807
申请日：2009-01-05
申请人： Michael Raymond Miller
发明人： Michael Raymond Miller
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/0016
摘要： Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.
摘要翻译：锁存器和类似电子设备的功耗降低。一方面，用于配置顺序逻辑的功耗的装置包括顺序逻辑器件，其包括第一锁存器，第二锁存器以及第一和第二使能输入。第一使能输入启用和禁用第一和第二锁存器，第二使能输入使能和禁止第二个锁存器，并且不影响第一个锁存器。第一使能输入具有比第二使能输入更早要求的信号到达时间，以在特定时钟周期内有效。一个电路在顺序逻辑器件的较低工作频率下，将顺序逻辑器件配置在工作时间以消耗更少的功率，并在更高的工作频率下消耗更多的功率。

3. 发明申请

US20090115454A1 Method and System for Reducing Power Consumption with Configurable Latches and Registers 失效
标题翻译：使用可配置的锁存器和寄存器降低功耗的方法和系统
公开(公告)号：US20090115454A1
公开(公告)日：2009-05-07
申请号：US12348807
申请日：2009-01-05
申请人： Michael Raymond Miller
发明人： Michael Raymond Miller
IPC分类号： G06F7/38
CPC分类号： H03K19/0016
摘要： Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.
摘要翻译：锁存器和类似电子设备的功耗降低。一方面，用于配置顺序逻辑的功耗的装置包括顺序逻辑器件，其包括第一锁存器，第二锁存器以及第一和第二使能输入。第一使能输入启用和禁用第一和第二锁存器，第二使能输入使能和禁止第二个锁存器，并且不影响第一个锁存器。第一使能输入具有比第二使能输入更早要求的信号到达时间，以在特定时钟周期内有效。一个电路在顺序逻辑器件的较低工作频率下，将顺序逻辑器件配置在工作时间以消耗更少的功率，并在更高的工作频率下消耗更多的功率。

4. 发明授权

US07474123B1 Method for reducing power consumption with configurable latches and registers 失效
标题翻译：用配置锁存器和寄存器降低功耗的方法
公开(公告)号：US07474123B1
公开(公告)日：2009-01-06
申请号：US11839829
申请日：2007-08-16
申请人： Michael Raymond Miller
发明人： Michael Raymond Miller
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/0016
摘要： Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.
摘要翻译：锁存器和类似电子设备的功耗降低。一方面，用于配置顺序逻辑的功耗的装置包括顺序逻辑器件，其包括第一锁存器，第二锁存器以及第一和第二使能输入。第一使能输入启用和禁用第一和第二锁存器，第二使能输入使能和禁止第二个锁存器，并且不影响第一个锁存器。第一使能输入具有比第二使能输入更早要求的信号到达时间，以在特定时钟周期内有效。一个电路在顺序逻辑器件的较低工作频率下，将顺序逻辑器件配置在工作时间以消耗更少的功率，并在更高的工作频率下消耗更多的功率。

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