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1. 发明授权

US06055584A Processor local bus posted DMA FlyBy burst transfers 失效
标题翻译：处理器本地总线发送DMA FlyBy突发传输
公开(公告)号：US06055584A
公开(公告)日：2000-04-25
申请号：US975540
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
摘要翻译：提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。从总线控制器还耦合到存储器单元。存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

2. 发明授权

US08725488B2 Method and apparatus for adaptive voltage scaling based on instruction usage 失效
标题翻译：基于指令使用的自适应电压缩放的方法和装置
公开(公告)号：US08725488B2
公开(公告)日：2014-05-13
申请号：US11828782
申请日：2007-07-26
申请人： Richard Gerard Hofmann , Jeffrey Todd Bridges
发明人： Richard Gerard Hofmann , Jeffrey Todd Bridges
IPC分类号： G06F9/455 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.
摘要翻译：不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。为了降低电源电压，使用自适应电压缩放方法。从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。降低电压可以根据指令集的使用量减少功耗，从而延长电池寿命。

3. 发明申请

US20090031155A1 Method and Apparatus for Adaptive Voltage Scaling Based on Instruction Usage 失效
标题翻译：基于指令使用的自适应电压调节方法与装置
公开(公告)号：US20090031155A1
公开(公告)日：2009-01-29
申请号：US11828782
申请日：2007-07-26
申请人： Richard Gerard Hofmann , Jeffrey Todd Bridges
发明人： Richard Gerard Hofmann , Jeffrey Todd Bridges
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.
摘要翻译：不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。为了降低电源电压，使用自适应电压缩放方法。从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。基于指令集的使用，电压的降低可以减少功耗，从而延长电池寿命。

4. 发明授权

US6081860A Address pipelining for data transfers 失效
标题翻译：地址流水线进行数据传输
公开(公告)号：US6081860A
公开(公告)日：2000-06-27
申请号：US975545
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.
摘要翻译：一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

5. 发明申请

US20130019117A1 Methods and Apparatus for Voltage Scaling 有权
标题翻译：电压调节的方法和装置
公开(公告)号：US20130019117A1
公开(公告)日：2013-01-17
申请号：US13183129
申请日：2011-07-14
申请人： Gerald Paul Michalak , Jeffrey Todd Bridges
发明人： Gerald Paul Michalak , Jeffrey Todd Bridges
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/26 , Y02D10/172
摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.
摘要翻译：提供了电压缩放的方法和装置。在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。时钟频率和电源电压可以在一段持续时间内保持基本上恒定。如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。确定运行极限后，将电源电压调整到运行极限内。

6. 发明授权

US08008961B2 Adaptive clock generators, systems, and methods 有权
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：US08008961B2
公开(公告)日：2011-08-30
申请号：US12637321
申请日：2009-12-14
申请人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
发明人： Manish Garg , Chiaming Chai , Jeffrey Todd Bridges
IPC分类号： H03K3/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

7. 发明授权

US07821350B2 Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors 有权
标题翻译：用于微处理器的锁相环的动态频率缩放的方法和装置
公开(公告)号：US07821350B2
公开(公告)日：2010-10-26
申请号：US11624995
申请日：2007-01-19
申请人： Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
发明人： Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
IPC分类号： H03L7/04
CPC分类号： H03L7/189 , H03L2207/06
摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
摘要翻译：公开了一种采用多个振荡器复合器的锁相环。锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

8. 发明授权

US07210024B2 Conditional instruction execution via emissary instruction for condition evaluation 有权
标题翻译：有条件的指令通过使用指令执行条件评估
公开(公告)号：US07210024B2
公开(公告)日：2007-04-24
申请号：US11055919
申请日：2005-02-10
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译：通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。在基本指令停止的情况下执行执行指令。使者指令评估条件并将条件评估报告回基本指令。基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。在任一情况下，可以解决以下指令的依赖性。

9. 发明授权

US07698536B2 Method and system for providing an energy efficient register file 有权
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：US07698536B2
公开(公告)日：2010-04-13
申请号：US11201542
申请日：2005-08-10
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Jeffrey Todd Bridges , Michael Scott McIlvaine , Gregory Christopher Burda
IPC分类号： G06F9/00
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

10. 发明申请

US20080281996A1 Latency Insensitive FIFO Signaling Protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US20080281996A1
公开(公告)日：2008-11-13
申请号：US12179970
申请日：2008-07-25
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

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