专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07913021B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07913021B2
公开(公告)日：2011-03-22
申请号：US11565041
申请日：2006-11-30
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

2. 发明授权

US08615638B2 Memory controllers, systems and methods for applying page management policies based on stream transaction information 有权
标题翻译：基于流交易信息应用页面管理策略的内存控制器，系统和方法
公开(公告)号：US08615638B2
公开(公告)日：2013-12-24
申请号：US12900857
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

3. 发明授权

US07209998B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07209998B2
公开(公告)日：2007-04-24
申请号：US10921053
申请日：2004-08-17
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

4. 发明授权

US6047336A Speculative direct memory access transfer between slave devices and memory 失效
标题翻译：从设备和存储器之间的直接存储器访问传输
公开(公告)号：US6047336A
公开(公告)日：2000-04-04
申请号：US39645
申请日：1998-03-16
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.
摘要翻译： DMA控制器响应来自从设备的数据传输请求，启动存储器传送周期并在数据传输完成时通知从设备。为了避免内部总线上的死时钟周期，DMA控制器在通知后启动推测数据传输周期。如果从设备在预定时间内没有请求另一个数据传输，则DMA控制器中止推测数据传输周期。

5. 发明申请

US20120089789A1 Memory Controllers, Systems and Methods for Applying Page Management Policies Based on Stream Transaction Information 有权
标题翻译：基于流交易信息应用页面管理策略的内存控制器，系统和方法
公开(公告)号：US20120089789A1
公开(公告)日：2012-04-12
申请号：US12900857
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

6. 发明申请

US20120089759A1 Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s) 审中-公开
标题翻译：基于与流事务相关的信息仲裁流事务
公开(公告)号：US20120089759A1
公开(公告)日：2012-04-12
申请号：US12900800
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： Devices, systems, methods, and computer-readable mediums for arbitrating stream transactions based on information related to the stream transactions are disclosed. A stream transaction is a superset of burst access types to facilitate efficient bulk transfers of data. In one embodiment, an arbiter is provided that arbitrates bus transactions between a plurality of devices coupled to a bus competing for resources accessible through the bus. To efficiently arbitrate stream transactions requested on the bus, the arbiter is configured to use information related to the stream transactions to provide a view of future bus traffic on the bus. The arbiter is configured to use this stream transaction information to apply bus arbitration policies for arbitrating stream transactions. In this example, the bus arbitration policy can be adjusted for stream transactions based on the stream transaction information, if necessary, for the arbiter to attempt to meet a parameter(s) for completing the stream transactions.
摘要翻译：公开了用于基于与流事务相关的信息来仲裁流事务的设备，系统，方法和计算机可读介质。流事务是突发访问类型的超集，以便于数据的高效批量传输。在一个实施例中，提供仲裁器，其仲裁耦合到总线的多个设备之间的总线事务，该总线竞争通过总线可访问的资源。为了有效地仲裁在总线上请求的流事务，仲裁器被配置为使用与流事务相关的信息来提供总线上未来总线流量的视图。仲裁器被配置为使用该流事务信息来应用用于仲裁流事务的总线仲裁策略。在该示例中，如果需要，可以基于流交易信息来调整总线仲裁策略，以便仲裁者尝试满足用于完成流事务的参数。

7. 发明授权

US08028143B2 Method and apparatus for transmitting memory pre-fetch commands on a bus 有权
标题翻译：一种用于在总线上传送存储器预取命令的方法和装置
公开(公告)号：US08028143B2
公开(公告)日：2011-09-27
申请号：US10929127
申请日：2004-08-27
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F12/0215 , G06F13/161
摘要： A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.
摘要翻译：公开了一种处理系统和方法，其中处理器可以被配置为预测将需要数据的存储器的地址，向存储器控制器发送在存储器的预测地址处的数据的预取命令，并且发送到如果需要数据，存储器控制器对存储器的预测地址处的数据的读请求。

8. 发明授权

US07617343B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07617343B2
公开(公告)日：2009-11-10
申请号：US11070016
申请日：2005-03-02
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/42 , G06F13/00 , G06F13/36 , H04Q1/30 , H04L1/18
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有发送和接收通道。发射信道可以具有多个子信道。发送组件可以被配置为在每个子信道上广播包括读取和写入地址位置，读取和写入控制信号以及每个子信道上的写入数据的信息。接收组件可以被配置为存储写入数据并且响应于在任何子信道上广播的信息来检索读取数据，并且将接收信道上检索到的读取数据广播到发送组件。发送组件还可以被配置为向每个子信道的接收组件提供独立的信令，独立信令足以允许接收组件确定在每个子信道上广播的信息的类型。

9. 发明授权

US06504854B1 Multiple frequency communications 失效
标题翻译：多频通讯
公开(公告)号：US06504854B1
公开(公告)日：2003-01-07
申请号：US09058724
申请日：1998-04-10
申请人： Richard Gerard Hofmann , Mark Michael Schaffer , Thomas Andrew Sartorius
发明人： Richard Gerard Hofmann , Mark Michael Schaffer , Thomas Andrew Sartorius
IPC分类号： H04J306
CPC分类号： G06F13/4059
摘要： A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.
摘要翻译：提供了一种用于处理系统等的通信系统，用于在与第二数据总线相关联的第一数据总线和外围设备之间执行数据传输操作，其中第一数据总线以第一时钟速度操作，并且其中第二数据总线数据总线运行。以与第一时钟速度不同的第二时钟速度和第一时钟速度的1 / N整数倍。接收与第二时钟速度相关联的采样信号，并且响应于采样信号动态地调整外围控制器的状态机的操作速度，使得外围控制器的状态机以第二时钟速度工作并导致在第二数据总线上的操作以第二时钟速度同步地发生。

10. 发明授权

US6032238A Overlapped DMA line transfers 失效
标题翻译：重叠的DMA线路传输
公开(公告)号：US6032238A
公开(公告)日：2000-02-29
申请号：US20123
申请日：1998-02-06
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.
摘要翻译：提供了允许DMA线读取和行写入周期重叠的方法和装置。在示例性实施例中，PLB线读取字地址总线与DMA控制器边带信号一起使用，以检测在线读取周期完成之前允许DMA控制器开始行写入一个周期所需的条件。当读取多字行传输的第一个字时，设置一个参考位。边缘定时信号在读周期完成之前一个周期产生，表示只读一行读取数据相位。如果要在存储器中写入的第一个字已经被读取或在生成定时信号时可用，则在存储器读取传送的最后阶段之前开始写入操作，并且读取和写入操作重叠，从而完成如果顺序完成，则读取/写入传输的循环次数比读取和写入传输周期的总和少。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式