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1. 发明授权

US5926831A Methods and apparatus for control of speculative memory accesses 失效
标题翻译：用于控制存储器访问的方法和装置
公开(公告)号：US5926831A
公开(公告)日：1999-07-20
申请号：US731350
申请日：1996-10-11
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer , James N. Dieffenderfer
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0215
摘要： A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.
摘要翻译：一种动态配置的存储器控制器，用于防止对非良好行为内存的推测性内存访问。可以通过向存储器控制器提供与存储器请求相关联的保护信息来实现存储器控制器的这种动态配置。当保护信息指示存储器请求是非良好的存储器时，存储器控制器可以防止推测存储器访问。提供给存储器控制器的保护信息可以包括与提供给存储器控制器的每个存储器请求相关联的保护信息。

2. 发明授权

US5925118A Methods and architectures for overlapped read and write operations 失效
标题翻译：用于重叠读写操作的方法和体系结构
公开(公告)号：US5925118A
公开(公告)日：1999-07-20
申请号：US729555
申请日：1996-10-11
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/364 , G06F13/14
CPC分类号： G06F13/364
摘要： A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions. In a preferred embodiment of the present invention, the master function and the slave function are further connected by a plurality of transfer qualifier signals which may specify whether the operation is a read or a write operation, the size of the transfer, the direction of the transfer or the type of transfer so as to further facilitate multiple cycle transfers with a single address specified on the single address bus.
摘要翻译：通信系统和通信方法，其包括通过单个地址总线，写数据总线和读数据总线连接到主功能的从功能，以便允许在主功能和从机之间重叠多周期读和写操作功能。优选地，通信系统包括通过单个地址总线，写数据总线和读数据总线连接到主功能的多个从功能。多个主功能可以通过总线仲裁器连接到从属功能，总线仲裁器通过地址总线，写数据总线和用于每个主功能的读数据总线连接到多个主功能。总线仲裁器从多个主功能接收通信操作的请求，并且选择性地将通信操作发送到从属功能。在本发明的优选实施例中，主功能和从功能还通过多个传输限定符信号进一步连接，传输限定符可以指定操作是读还是写操作，传输的大小，传输的方向传输或传输类型，以便通过在单个地址总线上指定的单个地址来进一步促进多个周期传输。

3. 发明授权

US6081860A Address pipelining for data transfers 失效
标题翻译：地址流水线进行数据传输
公开(公告)号：US6081860A
公开(公告)日：2000-06-27
申请号：US975545
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Jeffrey Todd Bridges , Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.
摘要翻译：一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

4. 发明授权

US5862353A Systems and methods for dynamically controlling a bus 失效
标题翻译：用于动态控制总线的系统和方法
公开(公告)号：US5862353A
公开(公告)日：1999-01-19
申请号：US823736
申请日：1997-03-25
申请人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Juan Guillermo Revilla , Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F13/362 , G06F13/364 , G06F13/372 , G06F13/36
CPC分类号： G06F13/364
摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in bus usage. Devices submit a priority level along with a bus request to a bus controller. Upon receiving multiple requests, an arbiter of the bus controller compares the priority levels associated with the different bus requests and grants control of the bus to the device having the highest priority level. During each cycle that a device has control of the bus, a feedback logic circuit of the bus controller determines whether other bus requests are pending, and if so, determines the highest pending request priority level. Signals corresponding to the results of these determinations are fed back to each device. The device having control of the bus uses the combination of the currently pending request priority level and the device's own latency timer to determine whether it should maintain control of the bus or relinquish control of the bus.
摘要翻译：具有访问公共共享总线的多个设备的计算机系统中的总线性能可以通过增加吞吐量和减少等待时间来改善，同时考虑总线使用的动态变化。设备将总线请求提交给总线控制器。在接收到多个请求时，总线控制器的仲裁器比较与不同总线请求相关联的优先级，并将总线的控制授权给具有最高优先级的设备。在每个周期中，器件具有对总线的控制，总线控制器的反馈逻辑电路确定其他总线请求是否正在等待，如果是，则确定最高待机请求优先级。与这些测定结果相对应的信号被反馈给每个设备。具有总线控制的设备使用当前挂起的请求优先级和设备自身的延迟定时器的组合来确定其是否应该保持对总线的控制或放弃对总线的控制。

5. 发明授权

US5884051A System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities 失效
标题翻译：基于固定和动态优先级灵活控制总线访问的系统，方法和计算机程序产品
公开(公告)号：US5884051A
公开(公告)日：1999-03-16
申请号：US874639
申请日：1997-06-13
申请人： Mark Michael Schaffer , James N. Dieffenderfer , Edward Hammond Green, III , Juan Guillermo Revilla
发明人： Mark Michael Schaffer , James N. Dieffenderfer , Edward Hammond Green, III , Juan Guillermo Revilla
IPC分类号： G06F13/364 , G06F13/18 , G06F13/362
CPC分类号： G06F13/364
摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.
摘要翻译：可以通过提供灵活的总线仲裁器来改进具有访问公共共享总线的多个设备的计算机系统中的总线性能。总线访问使用总线仲裁器进行控制，总线仲裁器可操作地连接到每个设备。每个设备具有固定的可编程优先级和与之相关联的动态优先级。动态优先级包括仲裁器动态优先级和主动态优先级。基于可编程固定优先级与与每个设备相关联的动态优先级的组合来控制设备对总线的访问。虽然由仲裁器设置的可编程固定优先级和仲裁器动态优先级不受主控制，主动态优先级由主控制。如果启用主动态优先级，它将覆盖仲裁器动态优先级。如果未启用主动态优先级，但启用仲裁动态优先级，则主动态优先级将覆盖可编程固定优先级。

6. 发明授权

US06504854B1 Multiple frequency communications 失效
标题翻译：多频通讯
公开(公告)号：US06504854B1
公开(公告)日：2003-01-07
申请号：US09058724
申请日：1998-04-10
申请人： Richard Gerard Hofmann , Mark Michael Schaffer , Thomas Andrew Sartorius
发明人： Richard Gerard Hofmann , Mark Michael Schaffer , Thomas Andrew Sartorius
IPC分类号： H04J306
CPC分类号： G06F13/4059
摘要： A communication system is provided for use in processing systems and the like for carrying out data transfer operations between a first data bus and a peripheral device associated with a second data bus, wherein the first data bus operates at a first clock speed and wherein the second data bus operates. at a second clock speed which is different from the first clock speed and a 1/N integer multiple of the first clock speed. A sample signal associated with the second clock speed is received and the speed of operation of a state machine of a peripheral controller is dynamically adjusted in response to the sample signal such that the state machine of the peripheral controller operates at the second clock speed and causes operations on the second data bus to occur synchronously at the second clock speed.
摘要翻译：提供了一种用于处理系统等的通信系统，用于在与第二数据总线相关联的第一数据总线和外围设备之间执行数据传输操作，其中第一数据总线以第一时钟速度操作，并且其中第二数据总线数据总线运行。以与第一时钟速度不同的第二时钟速度和第一时钟速度的1 / N整数倍。接收与第二时钟速度相关联的采样信号，并且响应于采样信号动态地调整外围控制器的状态机的操作速度，使得外围控制器的状态机以第二时钟速度工作并导致在第二数据总线上的操作以第二时钟速度同步地发生。

7. 发明授权

US5848436A Method and apparatus for efficiently providing data from a data storage medium to a processing entity 失效
标题翻译：用于从数据存储介质向处理实体有效地提供数据的方法和装置
公开(公告)号：US5848436A
公开(公告)日：1998-12-08
申请号：US612631
申请日：1996-03-06
申请人： Thomas Andrew Sartorius , Mark Michael Schaffer
发明人： Thomas Andrew Sartorius , Mark Michael Schaffer
IPC分类号： G06F9/34 , G06F12/00 , G06F12/06
CPC分类号： G06F9/34
摘要： A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.
摘要翻译：当处理器请求当前未存储在高速缓冲存储器中的特定字时，完成一种使数据线以与处理器修改的小端模式或大端操作模式的数据结构一致的顺序取出的方法和装置。请求包括特定字的地址，并且提供关于处理器是否以修改的小端模式或大端模式操作的指示。存储器管理器在接收到请求时，基于地址和操作模式从存储器（存储设备）检索一行数据。例如，当使用大端模式时，使用目标字第一排序检索数据行，并且当使用修改的小端模式时，使用反向目标字第一排序来检索数据行。

8. 发明授权

US07913021B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07913021B2
公开(公告)日：2011-03-22
申请号：US11565041
申请日：2006-11-30
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

9. 发明授权

US6052745A System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers 失效
标题翻译：用于在固定长度突发传输中在上一周期之前和之后一个周期断言突发终止信号和突发完整信号的系统
公开(公告)号：US6052745A
公开(公告)日：2000-04-18
申请号：US96943
申请日：1998-06-12
申请人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
发明人： Michael Raymond Miller , John Patrick McCardle, II , Michael Patrick Muhlada , Mark Michael Schaffer , Christopher Randall Starr
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and is optional so a master and slave who use the protocol of the present invention is compatible with masters and slaves who do not.
摘要翻译：本发明提供了一种在数据处理系统内的总线上的数据的固定长度突发的方法和系统。根据本发明的方法和系统提供突发传输协议，其包括当至少一个主设备从至少一个主设备到至少一个从设备的信号时提供固定长度的数据突发数据长度信息设备请求固定长度的数据突发。它还包括在固定长度脉冲串中的最后一个周期之前一个周期由至少一个从设备断言突发终止信号，以及在固定长度脉冲串中的最后一个周期期间断言突发完成信号以进行写入基于信号的值，在针对读取脉冲串的固定长度脉冲串中的最后一个周期之前的一个周期。该突发传输协议允许在主机和从机之间的本地总线上执行最大长度的突发传输，而在传输之后不会造成死循环损坏。这样可以提高局部总线上数据吞吐量的效率和性能，而无需增加频率。本发明不需要新的信号并且是可选的，所以使用本发明的协议的主设备和从设备与没有的主设备和从设备兼容。

10. 发明授权

US08615638B2 Memory controllers, systems and methods for applying page management policies based on stream transaction information 有权
标题翻译：基于流交易信息应用页面管理策略的内存控制器，系统和方法
公开(公告)号：US08615638B2
公开(公告)日：2013-12-24
申请号：US12900857
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

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