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11. 发明申请

US20060278917A1 Floating gate structures 审中-公开
标题翻译：浮门结构
公开(公告)号：US20060278917A1
公开(公告)日：2006-12-14
申请号：US11508090
申请日：2006-08-22
申请人： Leonard Forbes , Jerome Eldridge , Kie Ahn
发明人： Leonard Forbes , Jerome Eldridge , Kie Ahn
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , G11C16/0416 , H01L27/115 , H01L29/42324 , H01L29/51 , H01L29/511
摘要： Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
摘要翻译：提供了具有低隧道势垒隔离绝缘子的DEAPROM存储器的结构和方法。 DEAPROM存储器包括由衬底中的沟道区分隔开的第一源极/漏极区域和第二源极/漏极区域。浮动栅极与沟道区相对，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过具有小于1.5eV的隧道势垒的低隧道势垒栅极绝缘体与浮动栅极分离。低隧道势垒隔间绝缘体包括选自NiO，Al 2 O 3 O 3，Ta 2 O 3 O 3的金属氧化物绝缘体 > 5，TiO 2，ZrO 2，Nb 2 O 5，Y 3， 2个O 3，3个O 2，3个O 2，3个，3个，3个，3个，3个，3个， 3 Sr 3 O 3，SrTiO 3 3，PbTiO 3 3和PbZ 3 O 3。浮置栅极包括其上形成有金属层的多晶硅浮栅，该金属层与低隧道势垒隔间绝缘体接触。并且，控制栅极包括其上形成有金属层的多晶硅控制栅极，其与低隧道势垒隔离栅绝缘体接触。

12. 发明申请

US20060237768A1 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers 有权
标题翻译：可编程阵列逻辑或具有p沟道器件和不对称隧道势垒的存储器
公开(公告)号：US20060237768A1
公开(公告)日：2006-10-26
申请号：US11471348
申请日：2006-06-20
申请人： Leonard Forbes , Jerome Eldridge , Kie Ahn
发明人： Leonard Forbes , Jerome Eldridge , Kie Ahn
IPC分类号： H01L29/76
CPC分类号： H01L27/11556 , G11C16/0416 , H01L27/115 , H01L29/51 , H01L29/511 , H01L29/7881 , H01L29/7885
摘要： Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator.
摘要翻译：提供了具有p沟道器件的可编程阵列型逻辑和/或存储器的结构和方法以及非对称的低隧道势垒隔离绝缘体。可编程阵列型逻辑和/或存储器件包括具有由n型衬底中的p型沟道区分隔开的第一源极/漏极区域和第二源极/漏极区域的p沟道非易失性存储器。与p型沟道区相对的浮栅，并由栅极氧化物分离。控制门反对浮动门。控制栅极通过不对称的低隧道势垒栅极绝缘体与浮动栅极分离。非对称低隧道势垒隔间绝缘体包括选自Al 2 O 3 O 3，Ta 2 O 3的金属氧化物绝缘体， 5，TiO 2，ZrO 2，Nb 2 O 5，SrBi 2 TaTiO 3，PbTiO 3 3和PbZrO 3 3，3， / SUB>。浮置栅极包括其上形成有金属层的多晶硅浮栅，该金属层与低隧道势垒隔间绝缘体接触。并且，控制栅极包括具有金属层的多晶硅控制栅极，其与形成在浮栅上的金属层具有不同的功函数，形成在其上与低隧道势垒隔离栅绝缘体接触。

13. 发明申请

US20060145241A1 Non-planar flash memory array with shielded floating gates on silicon mesas 有权
公开(公告)号：US20060145241A1
公开(公告)日：2006-07-06
申请号：US11363730
申请日：2006-02-28
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L29/788
CPC分类号： G11C16/0408 , H01L27/11521 , H01L27/11551 , H01L27/11553
摘要： A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.

14. 发明申请

US20060043504A1 Atomic layer deposited titanium aluminum oxide films 有权
标题翻译：原子层沉积钛氧化铝薄膜
公开(公告)号：US20060043504A1
公开(公告)日：2006-03-02
申请号：US10931533
申请日：2004-08-31
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L21/0228 , C23C16/0281 , C23C16/40 , C23C16/45531 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/022 , H01L21/02337 , H01L21/28229 , H01L21/3141 , H01L21/3142 , H01L29/513 , H01L29/517
摘要： A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include conducting a number of annealing processes between a number of atomic layer deposition cycles for forming the metal oxide film. In an embodiment, a titanium aluminum oxide film is formed by depositing titanium and/or aluminum by atomic layer deposition onto a substrate surface. The deposited titanium and/or aluminum is annealed using atomic oxygen. After annealing, a layer of titanium aluminum oxide is formed on the annealed layer to form a contiguous layer of titanium aluminum oxide. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium aluminum oxide film, and methods for forming such structures.
摘要翻译：包含具有多个金属成分的原子层沉积的绝缘金属氧化物膜的电介质层和制造这种电介质层的方法产生用于各种电子器件的可靠的电介质层。实施例包括在用于形成金属氧化物膜的多个原子层沉积循环之间进行多个退火处理。在一个实施方案中，通过将原子层沉积物将钛和/或铝沉积在基材表面上形成钛氧化铝膜。使用原子氧退火沉积的钛和/或铝。退火后，在退火层上形成一层氧化钛钛，形成邻接的氧化钛钛层。实施例包括用于电容器，晶体管，存储器件和具有包含原子层沉积的钛铝氧化物膜的电介质层的电子系统的结构，以及用于形成这种结构的方法。

15. 发明申请

US20060002192A1 Integrated circuit memory device and method 有权
公开(公告)号：US20060002192A1
公开(公告)日：2006-01-05
申请号：US11212190
申请日：2005-08-26
申请人： Leonard Forbes , Jerome Eldridge , Kie Ahn
发明人： Leonard Forbes , Jerome Eldridge , Kie Ahn
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , G11C16/0416 , H01L27/115 , H01L29/42324 , H01L29/51 , H01L29/511
摘要： Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

16. 发明申请

US20060001082A1 Floating-gate field-effect transistors having doped aluminum oxide dielectrics 有权
标题翻译：具有掺杂的氧化铝电介质的浮栅场效应晶体管
公开(公告)号：US20060001082A1
公开(公告)日：2006-01-05
申请号：US11213156
申请日：2005-08-26
申请人： Kie Ahn , Leonard Forbes
发明人： Kie Ahn , Leonard Forbes
IPC分类号： H01L29/788
CPC分类号： H01L21/28211 , C23C14/081 , C23C14/58 , H01L21/02145 , H01L21/02178 , H01L21/02203 , H01L21/02269 , H01L21/02321 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/28273 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31695 , H01L27/10811 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L28/40 , H01L28/84 , H01L29/517 , H01L29/518 , H01L29/7883 , Y10T428/249953
摘要： Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.
摘要翻译：具有多孔氧化铝层的掺杂氧化铝层及其制造方法。多孔氧化铝层可以通过蒸发物理气相沉积技术形成，以便于形成高纯度的氧化铝层。掺杂剂材料嵌入在多孔氧化铝层的孔中并随后转变为电介质形式。可以在形成期间控制多孔氧化铝层的孔隙率，以便于控制掺杂的氧化铝层的掺杂水平。这种掺杂的氧化铝层可用作各种集成电路器件中的栅极电介质层，隔间电介质层和电容器介电层。

17. 发明申请

US20050205900A1 Semiconductor constructions and transistor gates 有权
标题翻译：半导体结构和晶体管栅极
公开(公告)号：US20050205900A1
公开(公告)日：2005-09-22
申请号：US11126455
申请日：2005-05-10
申请人： Leonard Forbes , Kie Ahn , Luan Tran
发明人： Leonard Forbes , Kie Ahn , Luan Tran
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/94
CPC分类号： H01L29/4983 , H01L21/28052 , H01L21/28061 , H01L21/28247 , H01L21/28273 , H01L29/4941 , H01L29/6656
摘要： One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.
摘要翻译：本发明的一个方面包括形成半导体结构的方法。形成图案线以包括第一层和第二层。第一层包括硅，第二层包括金属。线具有包括第一层限定部分和第二层限定部分的至少一个侧壁边缘。沿着至少一个侧壁边缘形成第三层。第三层包括硅并沿着侧壁边缘的第一层限定部分和侧壁边缘的第二层限定部分。第三层的硅与第二层的金属反应，沿着侧壁边缘的第二层限定部分形成硅化物。去除第三层的硅以留下第一层的硅，第二层的金属和硅化物。

18. 发明申请

US20050190617A1 Folded bit line DRAM with vertical ultra thin body transistors 有权
标题翻译：带有垂直超薄体晶体管的折叠位线DRAM
公开(公告)号：US20050190617A1
公开(公告)日：2005-09-01
申请号：US11037831
申请日：2005-01-18
申请人： Leonard Forbes , Kie Ahn
发明人： Leonard Forbes , Kie Ahn
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/786 , G11C29/00
CPC分类号： H01L27/10823 , H01L27/10814 , H01L27/10876 , H01L27/10885 , H01L27/1203 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Further, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing alternating body regions of the single crystalline vertical transistors that are adjacent to the trench.
摘要翻译：提供折叠的位线DRAM装置。折叠位线DRAM器件包括存储器单元阵列。存储单元阵列中的每个存储单元包括从半导体衬底向外延伸的柱。每个柱包括单晶第一接触层和由氧化物层分离的单晶第二接触层。单柱垂直晶体管沿着柱的交替侧面在一排柱内形成。单晶垂直晶体管包括耦合到第一接触层的超薄单晶垂直第一源极/漏极区域，耦合到第二接触层的超薄单晶垂直第二源极/漏极区域，以及超薄单晶垂直体区域，其与氧化物层相对并耦合第一和第二源极/漏极区域。多个掩埋位线由单晶半导体材料形成并且设置在阵列存储单元中的柱下方，用于与存储器单元阵列中的相邻柱的第一接触层互连。此外，包括多个字线。每个字线与柱之间的沟槽中的多个掩埋位线正交地布置，用于寻址与沟槽相邻的单晶垂直晶体管的交替体区。

19. 发明申请

US20050186773A1 Methods and structures for metal interconnections in integrated circuits 有权
公开(公告)号：US20050186773A1
公开(公告)日：2005-08-25
申请号：US11104160
申请日：2005-04-12
申请人： Kie Ahn , Leonard Forbes , Paul Farrar
发明人： Kie Ahn , Leonard Forbes , Paul Farrar
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/7682 , H01L21/76886 , H01L23/53271 , H01L2221/1047 , H01L2924/0002 , Y10S438/933 , H01L2924/00
摘要： A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

20. 发明申请

US20050167723A1 Capacitor structures 审中-公开
公开(公告)号：US20050167723A1
公开(公告)日：2005-08-04
申请号：US11091285
申请日：2005-03-28
申请人： Leonard Forbes , Kie Ahn , Jerome Eldridge
发明人： Leonard Forbes , Kie Ahn , Jerome Eldridge
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/8242 , H01L29/76 , H01L27/108 , H01L31/119
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31683 , H01L21/318
摘要： The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into one or more of AlN, AlON, and AlO, with the transformed layer being a dielectric material over the first electrical node. A second electrical node is then formed over the dielectric material. The first electrical node, second electrical node and dielectric material together define at least a portion of the capacitor structure. The invention also pertains to a capacitor structure which includes a first electrical node, a second electrical node, and a dielectric material between the first and second electrical nodes. The dielectric material consists essentially of aluminum, oxygen and nitrogen.

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