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11. 发明授权

US5235199A Semiconductor memory with pad electrode and bit line under stacked capacitor 失效
标题翻译：具有焊盘电极的半导体存储器和堆叠电容器下的位线
公开(公告)号：US5235199A
公开(公告)日：1993-08-10
申请号：US831657
申请日：1992-02-07
申请人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
发明人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
IPC分类号： H01L27/108
CPC分类号： H01L27/10808 , Y10S257/905 , Y10S257/908
摘要： A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.
摘要翻译：半导体存储器具有许多存储单元，每个存储单元都包括晶体管和电容器在每个存储单元中，晶体管的源区和漏区中的一个连接到位线。位线形成在晶体管的上方。电容器包括形成在基板上的第一电容器电极和形成在涂覆在第一电容器电极的表面上的绝缘膜上的第二电容器电极。第一电容器电极连接到晶体管的源极和漏极区域中的另一个。第一电容器电极形成在位线上方。为了制造这样的半导体存储器，每个存储单元区域分别形成在基板的表面上。在存储单元区域上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。栅电极用作掩模以掺杂杂质以形成晶体管的源极和漏极区域。位线形成并连接到源区和漏区之一。第一电容器电极形成在位线上方并连接到源极和漏极区域中的另一个。在第一电容器电极的表面上形成绝缘膜，在绝缘膜上形成第二电容电极。

12. 发明授权

US06292390B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06292390B1
公开(公告)日：2001-09-18
申请号：US09755143
申请日：2001-01-08
申请人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
发明人： Koji Sakui , Takehiro Hasegawa , Shigeyoshi Watanabe , Fujio Masuoka , Tsuneaki Fuse , Toshiki Seshita , Seiichi Aritome , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： G11C1134
CPC分类号： H01L27/1025 , G11C11/39 , H01L29/36 , H01L29/42304 , H01L29/456 , H01L29/73 , H01L29/7322 , H01L29/885 , H03F3/04 , H03K3/021 , H03K17/567
摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE
摘要翻译：半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

13. 发明授权

US5561311A Semiconductor memory with insulation film embedded in groove formed on substrate 失效
标题翻译：具有绝缘膜的半导体存储器嵌入在衬底上形成的凹槽中
公开(公告)号：US5561311A
公开(公告)日：1996-10-01
申请号：US350113
申请日：1994-11-29
申请人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
发明人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10808 , Y10S257/905 , Y10S257/908
摘要： A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line. A first capacitor electrode is formed on the first insulating film, making electrical contact with the other of the source and drain regions of the memory cell through a contact hole opened through the first insulating film and insulated from the bit line by the first insulating film. A second capacitor electrode is formed on the first capacitor electrode with a second insulating film provided therebetween. The insulation film is embedded in a groove formed on the semiconductor substrate.
摘要翻译：具有存储单元的半导体存储器形成在半导体衬底上。每个存储单元都具有晶体管和电容器。晶体管包括沟道区域，漏极区域和源极区域，其在一条直线上排列并且被来自相邻单元格的绝缘膜绝缘。每个存储单元具有形成在沟道区上的栅电极，其间具有栅极绝缘膜。焊盘电极与存储单元的源区和漏区之一电接触并在绝缘膜上延伸。位线与上面的焊盘电极电接触，平行于线延伸并且与源区和漏区之一横向隔离。在位线上的半导体衬底上形成第一绝缘膜。第一电容器电极形成在第一绝缘膜上，通过穿过第一绝缘膜打开的接触孔与第一绝缘膜与位线绝缘而与存储单元的另一个源极和漏极区域电接触。在第一电容器电极上形成第二电容器电极，其间设置有第二绝缘膜。绝缘膜嵌入形成在半导体衬底上的沟槽中。

14. 发明授权

US5387532A Semiconductor memory having capacitor electrode formed above bit line 失效
标题翻译：具有形成在位线上方的电容电极的半导体存储器
公开(公告)号：US5387532A
公开(公告)日：1995-02-07
申请号：US103663
申请日：1993-08-10
申请人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
发明人： Takeshi Hamamoto , Fumio Horiguchi , Katsuhiko Hieda
IPC分类号： H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , Y10S257/905 , Y10S257/908
摘要： A semiconductor memory has many memory cells of which each has a transistor and a capacitor. In each memory cell, one of source and drain regions of the transistor is connected to a bit line formed above the transistor. The capacitor includes a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.
摘要翻译：半导体存储器具有许多存储单元，每个存储单元都具有晶体管和电容器。在每个存储单元中，晶体管的源极和漏极区之一连接到形成在晶体管上方的位线。电容器包括形成在基板上的第一电容器电极和形成在涂覆在第一电容器电极的表面上的绝缘膜上的第二电容器电极。第一电容器电极连接到晶体管的源极和漏极区域中的另一个。第一电容器电极形成在位线上方。为了制造这样的半导体存储器，每个存储单元区域分别形成在基板的表面上。在存储单元区域上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。栅电极用作掩模以掺杂杂质以形成晶体管的源极和漏极区域。位线形成并连接到源区和漏区之一。第一电容器电极形成在位线上方并连接到源极和漏极区域中的另一个。在第一电容器电极的表面上形成绝缘膜，在绝缘膜上形成第二电容电极。

15. 发明授权

US5371024A Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5371024A
公开(公告)日：1994-12-06
申请号：US947907
申请日：1992-09-21
申请人： Katsuhiko Hieda , Fumio Horiguchi , Hiroshi Takato , Fujio Masuoka
发明人： Katsuhiko Hieda , Fumio Horiguchi , Hiroshi Takato , Fujio Masuoka
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7834 , H01L29/1037 , H01L29/4236 , H01L29/456 , H01L29/66621
摘要： A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.
摘要翻译：半导体器件具有第一导电类型的半导体衬底，掩埋在形成于衬底的元件区域中的沟槽中的栅电极，第二导电类型的第一源极和漏极区域形成在两侧的半导体衬底的表面区域中的栅极电极，以及第二源极和漏极区域，其浓度高于第一源极和漏极区域的浓度，第二源极和漏极区域形成在栅极的任一侧上的半导体衬底的表面区域中电极，与栅极间隔开，并分别与第一源极和漏极区相邻。该半导体器件具有其中栅极深埋在衬底中的结构。因此，可以防止短的通道效应。埋在沟槽中的栅电极延伸穿过在半导体衬底的表面区域中形成的具有低杂质浓度的半导体区域，因此形成两个低杂质浓度区域。源区和漏区分别由低杂质浓度区和与其相邻的高杂质浓度区组成。低杂质浓度区域可显着提高漏极击穿电压。

16. 发明授权

US4979014A MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US4979014A
公开(公告)日：1990-12-18
申请号：US228519
申请日：1988-08-05
申请人： Katsuhiko Hieda , Fumio Horiguchi , Hidehiro Watanabe
发明人： Katsuhiko Hieda , Fumio Horiguchi , Hidehiro Watanabe
IPC分类号： H01L21/306 , H01L21/336 , H01L21/763 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7851 , H01L21/02063 , H01L21/763 , H01L29/66575 , H01L29/66795 , H01L29/78
摘要： An MOS transistor comprises a projection formed on the surface of a semiconductor substrate, a gate insulating film having an upper portion located on the upper surface of the projection and a pair of side portions extending from the upper portion and located on the side surfaces of the projection, source and drain regions located in the projection to sandwich the gate insulating film and to be exposed on the upper surface of the projection, and a gate electrode, having first and second portions respectively formed on the upper and side portions of the gate insulating film, for generating a depletion layer extending deeper into the projection than would a depletion layer generated by only the first portion, in the portion of the projection facing the first portion.
摘要翻译： MOS晶体管包括形成在半导体衬底的表面上的突起，具有位于突起的上表面上的上部的栅极绝缘膜和从上部延伸并位于该突起的侧表面上的一对侧部位于突起中的突起，源极和漏极区域，以夹持栅极绝缘膜并暴露在突起的上表面上;以及栅极，其具有分别形成在栅极绝缘的上部和侧部的第一和第二部分膜，用于在所述突起的面向所述第一部分的部分中产生比仅由所述第一部分产生的耗尽层更深地延伸到所述投影中的耗尽层。

17. 发明授权

US07042040B2 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US07042040B2
公开(公告)日：2006-05-09
申请号：US10762470
申请日：2004-01-23
申请人： Fumio Horiguchi
发明人： Fumio Horiguchi
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.

18. 发明申请

US20050141262A1 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US20050141262A1
公开(公告)日：2005-06-30
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

19. 发明授权

US5202751A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5202751A
公开(公告)日：1993-04-13
申请号：US905232
申请日：1992-06-29
申请人： Fumio Horiguchi
发明人： Fumio Horiguchi
IPC分类号： H01L23/522 , H01L23/528 , H01L27/02 , H01L27/06 , H01L27/108
CPC分类号： H01L27/108 , H01L23/5223 , H01L23/5286 , H01L27/0218 , H01L27/0688 , H01L2924/0002
摘要： A semiconductor integrated circuit having, for instance, a power source side conductor and an earth side conductor which are constructed such that the two conductors are formed into two layers mutually laminated in parallel, and a dielectric substance is interposed between the two layers for providing a capacitance. In this manner, the integrated circuit is operable such that a comparatively large capacitor is connected in the power source circuit thereof.
摘要翻译：一种具有例如电源侧导体和接地侧导体的半导体集成电路，其被构造成使得两个导体形成为彼此并联的两个层，并且介电物质插入在两个层之间以提供电容。以这种方式，集成电路可操作，使得在其电源电路中连接相对较大的电容器。

20. 发明授权

US06891225B2 Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US06891225B2
公开(公告)日：2005-05-10
申请号：US09947908
申请日：2001-09-07
申请人： Fumio Horiguchi , Takashi Ohsawa
发明人： Fumio Horiguchi , Takashi Ohsawa
IPC分类号： H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/42392 , H01L27/108 , H01L27/10873 , H01L27/10876 , H01L27/1203
摘要： A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to corresponding the drain diffusion layers, the bit lines being perpendicular to the word lines.
摘要翻译：一种半导体存储器件，包括：源极扩散层，形成在半导体衬底上并连接到固定电位线; 多个柱状半导体层，其以矩阵形式布置并形成在所述源极扩散层上，并且各自的一端共同连接到所述源极扩散层，所述柱状半导体层具有第一阈值电压的第一数据状态，所述第一阈值电压为多数载流子累积在柱状半导体层中的第二数据状态，以及具有第二阈值电压的第二数据状态，多数载流子从柱状半导体层放电; 多个漏极扩散层，各自形成在所述柱状半导体层的另一端; 多个栅极，每个栅极经由栅极绝缘膜与柱状半导体层相对，并连接到字线; 多个字线，各自连接到对应的栅电极; 以及多个位线，每个位线连接到对应的漏极扩散层，位线垂直于字线。

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