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1. 发明申请

US20050141262A1 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US20050141262A1
公开(公告)日：2005-06-30
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

2. 发明授权

US06891225B2 Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US06891225B2
公开(公告)日：2005-05-10
申请号：US09947908
申请日：2001-09-07
申请人： Fumio Horiguchi , Takashi Ohsawa
发明人： Fumio Horiguchi , Takashi Ohsawa
IPC分类号： H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/42392 , H01L27/108 , H01L27/10873 , H01L27/10876 , H01L27/1203
摘要： A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to corresponding the drain diffusion layers, the bit lines being perpendicular to the word lines.
摘要翻译：一种半导体存储器件，包括：源极扩散层，形成在半导体衬底上并连接到固定电位线; 多个柱状半导体层，其以矩阵形式布置并形成在所述源极扩散层上，并且各自的一端共同连接到所述源极扩散层，所述柱状半导体层具有第一阈值电压的第一数据状态，所述第一阈值电压为多数载流子累积在柱状半导体层中的第二数据状态，以及具有第二阈值电压的第二数据状态，多数载流子从柱状半导体层放电; 多个漏极扩散层，各自形成在所述柱状半导体层的另一端; 多个栅极，每个栅极经由栅极绝缘膜与柱状半导体层相对，并连接到字线; 多个字线，各自连接到对应的栅电极; 以及多个位线，每个位线连接到对应的漏极扩散层，位线垂直于字线。

3. 发明授权

US07075820B2 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US07075820B2
公开(公告)日：2006-07-11
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

4. 发明授权

US06548848B2 Semiconductor memory device 失效
公开(公告)号：US06548848B2
公开(公告)日：2003-04-15
申请号：US10005180
申请日：2001-12-03
申请人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
发明人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
IPC分类号： H01L27108
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10841 , H01L27/1203 , H01L29/7841
摘要： Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.

5. 发明授权

US07042040B2 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US07042040B2
公开(公告)日：2006-05-09
申请号：US10762470
申请日：2004-01-23
申请人： Fumio Horiguchi
发明人： Fumio Horiguchi
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10811 , H01L27/10885 , H01L27/10888
摘要： A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.

6. 发明授权

US5350708A Method of making dynamic random access semiconductor memory device 失效
标题翻译：制作动态随机存取半导体存储器件的方法
公开(公告)号：US5350708A
公开(公告)日：1994-09-27
申请号：US77744
申请日：1993-06-18
申请人： Atsushi Yagishita , Katsuhiko Hieda , Akihiro Nitayama , Fumio Horiguchi
发明人： Atsushi Yagishita , Katsuhiko Hieda , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10841 , H01L27/10823
摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.
摘要翻译：在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。在槽的中心部分形成场氧化膜。在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元阵列是结构化的

7. 发明授权

US5202751A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5202751A
公开(公告)日：1993-04-13
申请号：US905232
申请日：1992-06-29
申请人： Fumio Horiguchi
发明人： Fumio Horiguchi
IPC分类号： H01L23/522 , H01L23/528 , H01L27/02 , H01L27/06 , H01L27/108
CPC分类号： H01L27/108 , H01L23/5223 , H01L23/5286 , H01L27/0218 , H01L27/0688 , H01L2924/0002
摘要： A semiconductor integrated circuit having, for instance, a power source side conductor and an earth side conductor which are constructed such that the two conductors are formed into two layers mutually laminated in parallel, and a dielectric substance is interposed between the two layers for providing a capacitance. In this manner, the integrated circuit is operable such that a comparatively large capacitor is connected in the power source circuit thereof.
摘要翻译：一种具有例如电源侧导体和接地侧导体的半导体集成电路，其被构造成使得两个导体形成为彼此并联的两个层，并且介电物质插入在两个层之间以提供电容。以这种方式，集成电路可操作，使得在其电源电路中连接相对较大的电容器。

8. 发明授权

US5049957A MOS type dynamic random access memory 失效
标题翻译： MOS型动态随机存取存储器
公开(公告)号：US5049957A
公开(公告)日：1991-09-17
申请号：US528086
申请日：1990-05-24
申请人： Satoshi Inoue , Akihiro Nitayama , Kazumasa Sunouchi , Fumio Horiguchi
发明人： Satoshi Inoue , Akihiro Nitayama , Kazumasa Sunouchi , Fumio Horiguchi
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： In a semiconductor memory device, a storage node electrode having a cavity is provided such that the inner surface of a storage node electrode is used as a capacitor electrode. In a DRAM fabricating method, a storage node electrode having a cavity is formed by laminating a first conductor layer, an insulating film and a second conductor layer, which in turn are patterned into a desired shape, depositing a third conductor layer on the three-layer pattern, performing anisotropic etching so as to cause the third conductor layer to remain only on the side walls of the pattern to thereby form a box-shaped conductor, forming an opening in a part of the box-shaped conductor, removing the insulating film by an etching to thereby form a cavity.
摘要翻译：在半导体存储器件中，具有空腔的存储节点电极被设置为使得存储节点电极的内表面用作电容器电极。在DRAM制造方法中，通过层叠第一导体层，绝缘膜和第二导体层来形成具有空腔的存储节点电极，第一导体层，绝缘膜和第二导体层又被图案化成所需形状，层状图案，进行各向异性蚀刻，以使第三导体层仅保留在图案的侧壁上，从而形成盒状导体，在盒状导体的一部分中形成开口，去除绝缘膜通过蚀刻从而形成空腔。

9. 发明授权

US5363325A Dynamic semiconductor memory device having high integration density 失效
标题翻译：具有高集成密度的动态半导体存储器件
公开(公告)号：US5363325A
公开(公告)日：1994-11-08
申请号：US907032
申请日：1992-07-01
申请人： Kazumasa Sunouchi , Tsuneaki Fuse , Akihiro Nitayama , Takehiro Hasegawa , Shigeyoshi Watanabe , Fumio Horiguchi , Katsuhiko Hieda
发明人： Kazumasa Sunouchi , Tsuneaki Fuse , Akihiro Nitayama , Takehiro Hasegawa , Shigeyoshi Watanabe , Fumio Horiguchi , Katsuhiko Hieda
IPC分类号： H01L27/10 , G11C11/403 , G11C11/404 , G11C11/408 , H01L27/07 , H01L27/108 , G11L11/24
CPC分类号： G11C11/404 , G11C11/403 , G11C11/408 , H01L27/07 , H01L27/108
摘要： A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.
摘要翻译：具有由MOS晶体管M1的衬底区域SUB形成的集电极，由MOS晶体管的漏极区域形成的基极和形成在基极上并连接到位线BL的发射极的双极晶体管Q1连接在位线 BL和由MOS晶体管M1形成的存储单元MC和电容器C1以及双极晶体管的电流放大操作用于数据读出。

10. 发明授权

US5258635A MOS-type semiconductor integrated circuit device 失效
标题翻译： MOS型半导体集成电路器件
公开(公告)号：US5258635A
公开(公告)日：1993-11-02
申请号：US754191
申请日：1991-08-28
申请人： Akihiro Nitayama , Hiroshi Takato , Fumio Horiguchi , Fujio Masuoka
发明人： Akihiro Nitayama , Hiroshi Takato , Fumio Horiguchi , Fujio Masuoka
IPC分类号： H01L27/092 , H01L27/11 , H01L29/78 , H01L29/26
CPC分类号： H01L27/0928 , H01L27/1104 , H01L29/7827 , Y10S257/904
摘要： A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.
摘要翻译：提供了一种MOS型半导体集成电路器件，其中MOS晶体管形成为垂直配置。 MOS晶体管由形成在基板上的柱层构成。柱层的外周面用于形成MOS晶体管的栅极。因此，可以在小的区域内获得其大的栅极宽度。结果，可以在保持规定的载流能力的同时显着地减小MOS晶体管的总芯片面积。

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