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11. 发明授权

US08592876B2 Micro-electro-mechanical system (MEMS) capacitive OHMIC switch and design structures 有权
标题翻译：微机电系统（MEMS）电容OHMIC开关和设计结构
公开(公告)号：US08592876B2
公开(公告)日：2013-11-26
申请号：US13342689
申请日：2012-01-03
申请人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
发明人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L29/80
CPC分类号： H01H1/0036 , B81B7/0006 , B81B2201/016 , G06F17/5063 , G06F17/5068 , H01P1/127
摘要： A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.
摘要翻译：提供了微机电系统（MEMS），形成MEMS和设计结构的方法。该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。该方法包括在绝缘体材料中形成至少一个通气孔以暴露第二牺牲材料的部分，以及通过通气孔去除第一和第二牺牲材料，以形成围绕布线层的空腔结构，并使信号线和一对电极在布线层下方。通气孔用密封材料密封。

12. 发明授权

US08436446B2 Method, structure, and design structure for a through-silicon-via Wilkinson power divider 有权
公开(公告)号：US08436446B2
公开(公告)日：2013-05-07
申请号：US13455725
申请日：2012-04-25
申请人： Hanyi Ding , Alvin J. Joseph , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Alvin J. Joseph , Wayne H. Woods, Jr.
IPC分类号： H01L27/08
CPC分类号： G06F17/5077 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01P5/16 , H01P11/007 , H01L2924/00
摘要： A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

13. 发明申请

US20130044838A1 LOAD TOLERANT VOLTAGE CONTROLLED OSCILLATOR (VCO), IC AND CMOS IC INCLUDING THE VCO 失效
标题翻译：包含VCO的负载电压控制振荡器（VCO），IC和CMOS IC
公开(公告)号：US20130044838A1
公开(公告)日：2013-02-21
申请号：US13211697
申请日：2011-08-17
申请人： Hanyi Ding , Pinping Sun , Hailing Wang
发明人： Hanyi Ding , Pinping Sun , Hailing Wang
IPC分类号： H04L27/06 , H03B5/08 , H03B5/12
CPC分类号： H03B5/1228 , H03B5/04 , H03B5/1212 , H03B5/1243 , H03B2200/0034 , H04L25/0264
摘要： A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance
摘要翻译：压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。多孔结构中的二极管在每个器件中偏置。储能电路仅通过FET漏极耦合到缓冲器到体电容

14. 发明授权

US08299566B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08299566B2
公开(公告)日：2012-10-30
申请号：US12188236
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L23/48 , H01L21/763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

15. 发明申请

US20120132992A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20120132992A1
公开(公告)日：2012-05-31
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

16. 发明申请

US20120032737A1 ON-CHIP MILLIMETER WAVE LANGE COUPLER 有权
标题翻译：片上微米波浪耦合器
公开(公告)号：US20120032737A1
公开(公告)日：2012-02-09
申请号：US13277265
申请日：2011-10-20
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H03D3/00 , H03F3/68
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

17. 发明授权

US08106728B2 Circuit structure and design structure for an optionally switchable on-chip slow wave transmission line band-stop filter and a method of manufacture 有权
标题翻译：用于可选择切换的片上慢波传输线带阻滤波器的电路结构和设计结构以及制造方法
公开(公告)号：US08106728B2
公开(公告)日：2012-01-31
申请号：US12424110
申请日：2009-04-15
申请人： Hanyi Ding , Kwan H. Lam , Guoan Wang , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Kwan H. Lam , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01P3/08 , H01P1/203
CPC分类号： H01P1/203 , Y10T29/49155
摘要： The present invention generally relates to a circuit structure, design structure and method of manufacturing a circuit, and more specifically to a circuit structure and design structure for an on-chip slow wave transmission line band-stop filter and a method of manufacture. A structure includes an on-chip transmission line stub comprising a conditionally floating structure structured to provide increased capacitance to the on-chip transmission line stub when the conditionally floating structure is connected to ground.
摘要翻译：本发明一般涉及一种电路结构，电路制造的设计结构和方法，更具体地涉及用于片上慢波传输线带阻滤波器的电路结构和设计结构以及制造方法。一种结构包括片上传输线短截线，其包括有条件浮动结构，其被构造为当有条件浮动结构连接到地时为片上传输线短截线提供增加的电容。

18. 发明授权

US07812694B2 Coplanar waveguide integrated circuits having arrays of shield conductors connected by bridging conductors 有权
标题翻译：具有通过桥接导体连接的屏蔽导体阵列的共面波导集成电路
公开(公告)号：US07812694B2
公开(公告)日：2010-10-12
申请号：US12061950
申请日：2008-04-03
申请人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
发明人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： Coplanar waveguide structures and design structures for radiofrequency and microwave integrated circuits. The coplanar waveguide structure includes a signal conductor and ground conductors generally coplanar with the signal conductor. The signal conductor is disposed between upper and lower arrays of substantially parallel shield conductors. Conductive bridges, which are electrically isolated from the signal conductor, are located laterally between the signal conductor and each of the ground conductors. Pairs of the conductive bridges connect one of the shield conductors in the first array with one of the shield conductors in the second array to define closed loops encircling the signal line.
摘要翻译：射频和微波集成电路的共面波导结构和设计结构。共面波导结构包括信号导体和与信号导体大致共面的接地导体。信号导体设置在基本上平行的屏蔽导体的上和下阵列之间。与信号导体电隔离的导电桥横向位于信号导体和每个接地导体之间。一对导电桥将第一阵列中的一个屏蔽导体与第二阵列中的一个屏蔽导体连接，以限定围绕信号线的闭环。

19. 发明申请

US20100035390A1 METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成高性能FET和高电压FET的方法
公开(公告)号：US20100035390A1
公开(公告)日：2010-02-11
申请号：US12188366
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823462 , H01L21/823481 , H01L27/1203 , H01L27/1207
摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.
摘要翻译：保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

20. 发明申请

US20100032811A1 THROUGH WAFER VIAS AND METHOD OF MAKING SAME 有权
标题翻译：通过WAVER VIAS及其制作方法
公开(公告)号：US20100032811A1
公开(公告)日：2010-02-11
申请号：US12188241
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/76802 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。该结构包括：具有顶表面和相对底表面的半导体衬底; 以及贯穿晶片通孔的阵列，其包括至少一个导电的通过晶片通孔和至少一个非导电的通过晶片通孔，每个通过晶片通孔的通过晶片通孔的阵列从顶表面延伸到底表面所述衬底，所述至少一个导电通孔与所述衬底电隔离。

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