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1. 发明申请

US20130044838A1 LOAD TOLERANT VOLTAGE CONTROLLED OSCILLATOR (VCO), IC AND CMOS IC INCLUDING THE VCO 失效
标题翻译：包含VCO的负载电压控制振荡器（VCO），IC和CMOS IC
公开(公告)号：US20130044838A1
公开(公告)日：2013-02-21
申请号：US13211697
申请日：2011-08-17
申请人： Hanyi Ding , Pinping Sun , Hailing Wang
发明人： Hanyi Ding , Pinping Sun , Hailing Wang
IPC分类号： H04L27/06 , H03B5/08 , H03B5/12
CPC分类号： H03B5/1228 , H03B5/04 , H03B5/1212 , H03B5/1243 , H03B2200/0034 , H04L25/0264
摘要： A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance
摘要翻译：压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。多孔结构中的二极管在每个器件中偏置。储能电路仅通过FET漏极耦合到缓冲器到体电容

2. 发明授权

US08514028B2 Load tolerant voltage controlled oscillator (VCO), IC and CMOS IC including the VCO 失效
标题翻译：负载容限压控振荡器（VCO），IC和CMOS IC包括VCO
公开(公告)号：US08514028B2
公开(公告)日：2013-08-20
申请号：US13211697
申请日：2011-08-17
申请人： Hanyi Ding , Pinping Sun , Hailing Wang
发明人： Hanyi Ding , Pinping Sun , Hailing Wang
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/04 , H03B5/1212 , H03B5/1243 , H03B2200/0034 , H04L25/0264
摘要： A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance.
摘要翻译：压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。多孔结构中的二极管在每个器件中偏置。储能电路仅通过FET漏极耦合到缓冲器到体电容。

3. 发明授权

US08779870B2 Low phase variation CMOS digital attenuator 有权
标题翻译：低相位差CMOS数字衰减器
公开(公告)号：US08779870B2
公开(公告)日：2014-07-15
申请号：US13253260
申请日：2011-10-05
申请人： Pinping Sun , Hanyi Ding , Wayne H. Woods, Jr.
发明人： Pinping Sun , Hanyi Ding , Wayne H. Woods, Jr.
IPC分类号： H03L5/00 , H03H7/24 , H01P1/22
CPC分类号： H01P1/22 , H03H7/07 , H03H7/24 , H03H11/245 , H03L5/00
摘要： A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.
摘要翻译：低相位变化衰减器使用组合的衰减路径和相位网络来显着地减小参考信号和衰减信号之间的相位误差而不降低插入损耗。电阻和电容器的并联接地与衰减晶体管串联使用，该衰减晶体管连接到两个电阻分压器的中间。两个电阻分压器包括两个串联连接的等电阻电阻。两个电阻分压器与参考晶体管并联连接，参考晶体管用作发射或衰减射频（RF）信号的主开关。

4. 发明授权

US08643191B2 On-chip radial cavity power divider/combiner 有权
标题翻译：片上径向腔功率分配器/组合器
公开(公告)号：US08643191B2
公开(公告)日：2014-02-04
申请号：US13358792
申请日：2012-01-26
申请人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, Jr.
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/481 , H01L23/66 , H01L2224/16225 , H01L2924/1305 , H01L2924/15311 , H01L2924/00
摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.
摘要翻译：公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

5. 发明申请

US20130193584A1 ON-CHIP RADIAL CAVITY POWER DIVIDER/COMBINER 有权
标题翻译：片上径向辐射功率分配器/组合器
公开(公告)号：US20130193584A1
公开(公告)日：2013-08-01
申请号：US13358792
申请日：2012-01-26
申请人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, JR.
发明人： Hanyi Ding , Pinping Sun , Guoan Wang , Wayne H. Woods, JR.
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L23/66 , H01L2224/16225 , H01L2924/1305 , H01L2924/15311 , H01L2924/00
摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.
摘要翻译：公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

6. 发明申请

US20130088403A1 Low Phase Variation CMOS Digital Attenuator 有权
标题翻译：低相位变化CMOS数字衰减器
公开(公告)号：US20130088403A1
公开(公告)日：2013-04-11
申请号：US13253260
申请日：2011-10-05
申请人： Pinping Sun , Hanyi Ding , Wayne H. Woods, JR.
发明人： Pinping Sun , Hanyi Ding , Wayne H. Woods, JR.
IPC分类号： H01Q1/50 , G06F17/50 , H01P1/22
CPC分类号： H01P1/22 , H03H7/07 , H03H7/24 , H03H11/245 , H03L5/00
摘要： A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.
摘要翻译：低相位变化衰减器使用组合的衰减路径和相位网络来显着地减小参考信号和衰减信号之间的相位误差而不降低插入损耗。电阻和电容器的并联接地与衰减晶体管串联使用，该衰减晶体管连接到两个电阻分压器的中间。两个电阻分压器包括两个串联连接的等电阻电阻。两个电阻分压器与参考晶体管并联连接，参考晶体管用作发射或衰减射频（RF）信号的主开关。

7. 发明授权

US08592876B2 Micro-electro-mechanical system (MEMS) capacitive OHMIC switch and design structures 有权
标题翻译：微机电系统（MEMS）电容OHMIC开关和设计结构
公开(公告)号：US08592876B2
公开(公告)日：2013-11-26
申请号：US13342689
申请日：2012-01-03
申请人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
发明人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L29/80
CPC分类号： H01H1/0036 , B81B7/0006 , B81B2201/016 , G06F17/5063 , G06F17/5068 , H01P1/127
摘要： A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.
摘要翻译：提供了微机电系统（MEMS），形成MEMS和设计结构的方法。该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。该方法包括在绝缘体材料中形成至少一个通气孔以暴露第二牺牲材料的部分，以及通过通气孔去除第一和第二牺牲材料，以形成围绕布线层的空腔结构，并使信号线和一对电极在布线层下方。通气孔用密封材料密封。

8. 发明授权

US08436446B2 Method, structure, and design structure for a through-silicon-via Wilkinson power divider 有权
公开(公告)号：US08436446B2
公开(公告)日：2013-05-07
申请号：US13455725
申请日：2012-04-25
申请人： Hanyi Ding , Alvin J. Joseph , Wayne H. Woods, Jr.
发明人： Hanyi Ding , Alvin J. Joseph , Wayne H. Woods, Jr.
IPC分类号： H01L27/08
CPC分类号： G06F17/5077 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01P5/16 , H01P11/007 , H01L2924/00
摘要： A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

9. 发明授权

US08299566B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08299566B2
公开(公告)日：2012-10-30
申请号：US12188236
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L23/48 , H01L21/763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

10. 发明申请

US20120175612A1 TEST STRUCTURE FOR DETERMINATION OF TSV DEPTH 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20120175612A1
公开(公告)日：2012-07-12
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

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