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    • 8. 发明授权
    • Techniques for adjusting clock signals to compensate for noise
    • 调整时钟信号以补偿噪声的技术
    • US09565036B2
    • 2017-02-07
    • US13378024
    • 2010-05-31
    • Jared ZerbePradeep BatraBrian Leibowitz
    • Jared ZerbePradeep BatraBrian Leibowitz
    • H04L7/00H04L25/00H04L25/40H04L25/02G06F1/10H03K5/1252
    • H04L25/0264G06F1/10H03K5/1252
    • A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
    • 第一集成电路(IC)具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中,边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路(IC)之间的数据传输中的高频抖动的影响。 在其他实施例中,电源电压用于在多个IC上产生时钟信号。