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11. 发明申请

US20050007178A1 Low-power, low-area power headswitch 有权
标题翻译：低功耗，低功耗头灯
公开(公告)号：US20050007178A1
公开(公告)日：2005-01-13
申请号：US10617897
申请日：2003-07-10
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： H03K17/06 , H03K17/16
CPC分类号： H03K17/063
摘要： An N-FET headswitch has improved performance (e.g., less leakage current, lower ON resistance, and smaller area) over a conventional P-FET headswitch. The N-FET headswitch includes at least one N-FET device and couples between a power supply and a load circuit, which may be, e.g., a microprocessor, a digital signal processor, or a memory unit. The headswitch couples the power supply to the load circuit when the headswitch is enabled and cuts off the power supply from the load circuit when disabled. A charge pump couples to the headswitch and provides a control signal. This control signal is sufficiently high when the headswitch is enabled to ensure that the N-FET device operates in a linear region and has a small drain to source voltage drop. The headswitch may be operated as a power switch or in a feedback configuration to implement a linear or a digital voltage regulator.
摘要翻译： N-FET头开关在传统的P-FET头开关上具有改进的性能（例如，更小的漏电流，更低的导通电阻和更小的面积）。 N-FET头开关包括至少一个N-FET器件，并且在电源和负载电路之间耦合，该电路可以是例如微处理器，数字信号处理器或存储器单元。当头部开关使能时，头部开关将电源耦合到负载电路，并在禁用时从负载电路切断电源。电荷泵耦合到头开关并提供控制信号。当使能头部开关以确保N-FET器件在线性区域中工作并且具有小的漏极到源极电压降时，该控制信号足够高。头开关可以作为电源开关或反馈配置来实现线性或数字电压调节器。

12. 发明授权

US07583555B2 Robust and Efficient dynamic voltage scaling for portable devices 有权
标题翻译：强大而有效的便携式设备的动态电压缩放
公开(公告)号：US07583555B2
公开(公告)日：2009-09-01
申请号：US10814935
申请日：2004-03-30
申请人： Inyup Kang , Karthikeyan Ethirajan , Matthew Levi Severson , Mohamed Elgebaly , Manoj Sachdev , Amr Fahim
发明人： Inyup Kang , Karthikeyan Ethirajan , Matthew Levi Severson , Mohamed Elgebaly , Manoj Sachdev , Amr Fahim
IPC分类号： G11C7/00 , G05F1/40
CPC分类号： G05F1/40 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.
摘要翻译：一方面，用于电压调节的方法和装置在一个方面使用特定于所讨论的集成器件的工艺分裂的最坏情况的电源电压。在另一方面，两相电压调节系统和方法识别与第一阶段中的集成电路器件系列相关的特征数据，并且识别在第二阶段中候选集成电路器件的相关联的工艺分组。然后使用来自第一阶段的表征数据来提供对应于候选设备的目标操作频率的电源电压。另一方面，混合电压调节器电路包括开环电路，其自动识别集成电路器件的工艺分离，并且允许调节器基于该工艺分离特有的特性数据修改供电电压，以及闭环电路调节电源电压。在一个实施例中，闭环电路包括关键路径副本，用于提供集成电路设备中的关键路径所需的估计工作频率。在一个实施例中，在关键路径和/或开环电路中可以使用环形振荡器电路。

13. 发明申请

US20050077934A1 Low-power direct digital synthesizer with analog interpolation 有权
标题翻译：具有模拟插补功能的低功耗直接数字合成器
公开(公告)号：US20050077934A1
公开(公告)日：2005-04-14
申请号：US10684797
申请日：2003-10-14
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： G06F1/02 , G06F1/08 , H03K3/017 , H03K5/00 , H03K5/135 , H03K5/156 , H03K23/68 , H03L7/081 , H03L7/06
CPC分类号： G06F1/022 , G06F1/08 , G06F2211/902 , H03K5/135 , H03K5/1565 , H03K2005/00032 , H03K2005/00071 , H03L7/0814
摘要： An MN counter with analog interpolation (an “MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.
摘要翻译：具有模拟插值的MN计数器（“MNA计数器”）包括MN计数器，乘法器，延迟发生器和电流发生器。 MN计数器接收输入时钟信号和M和N值，使用模N累加器为每个输入时钟周期累加M，并提供具有所需频率的累加器值和计数器信号。乘法器将累加器值乘以M的倒数，并提供L位控制信号。电流发生器实现电流锁定环路，为延迟发生器提供参考电流。延迟发生器采用差分设计实现，接收计数器信号和L位控制信号，比较基于计数器和控制信号产生的差分信号，并提供输出时钟信号。输出时钟信号的前沿具有由L位控制信号和参考电流确定的可变延迟。

14. 发明授权

US07365607B2 Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL) 有权
$Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL)$
标题翻译：低功耗，低抖动，小数N全数字锁相环（PLL）
公开(公告)号：US07365607B2
公开(公告)日：2008-04-29
申请号：US11463630
申请日：2006-08-10
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/085 , H03L7/187
摘要： A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.
摘要翻译：一种用于以低抖动合成具有低抖动的全数字分数N锁相环（PLL）电子电路的频率的方法，其适于合成具有低抖动的频率，其中所述电子电路包括数字相位频率检测器（DPFD）连接到数字环路滤波器（DLF），其中DPFD适于接收参考信号和反馈信号; 比较参考和反馈信号的相位和频率，以确定参考和反馈信号之间的相位和频率误差; 并提供包括多位输出的DPFD输出; 其中所述DLF适于接收和过滤所述DPFD输出并提供DLF输出，并且其中在每个参考周期更新所述DLF输出。

15. 发明授权

US07348839B2 Method and apparatus for DC offset cancellation in amplifiers 有权
标题翻译：放大器中DC偏移消除的方法和装置
公开(公告)号：US07348839B2
公开(公告)日：2008-03-25
申请号：US11466465
申请日：2006-08-23
申请人： Amr Fahim , Hassan Elwan , Aly Ismail
发明人： Amr Fahim , Hassan Elwan , Aly Ismail
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/45968 , H03F3/45977 , H03F2200/78 , H03F2203/45212 , H03F2203/45424 , H03F2203/45438 , H03F2203/45444 , H03F2203/45618
摘要： A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.
摘要翻译：在级联放大器中消除DC偏移误差的系统，电路和方法包括以任何级联和并联配置布置多个模拟电压和模拟电流放大器级; 在给定的放大器周围的反馈路径中可操作地连接反馈比较器和数字逻辑，其中数字逻辑包括实现包括固定切换和调制切换的自适应搜索算法的有限状态机; 可操作地连接放大器的差分输入端的开关以缩短放大器的两个输入端子; 对二进制加权元件执行固定切换，产生离散模拟步骤，用于改变放大器输入处的任何DC偏移电压和电流; 以及对用于改变DC偏移电压和电流中的任何一个的所有位的至少一个较低最低有效位（LSB）执行调制开关。

16. 发明申请

US20080048791A1 LOW-POWER, LOW-JITTER, FRACTIONAL-N ALL-DIGITAL PHASE-LOCKED LOOP (PLL) 有权
标题翻译：低功耗，低抖动，分数N全数字锁相环（PLL）
公开(公告)号：US20080048791A1
公开(公告)日：2008-02-28
申请号：US11463630
申请日：2006-08-10
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： H03L7/085
CPC分类号： H03L7/1976 , H03L7/085 , H03L7/187
摘要： A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.
摘要翻译：一种用于以低抖动合成具有低抖动的全数字分数N锁相环（PLL）电子电路的频率的方法，其适于合成具有低抖动的频率，其中所述电子电路包括数字相位频率检测器（DPFD）连接到数字环路滤波器（DLF），其中DPFD适于接收参考信号和反馈信号; 比较参考和反馈信号的相位和频率，以确定参考和反馈信号之间的相位和频率误差; 并提供包括多位输出的DPFD输出; 其中所述DLF适于接收和过滤所述DPFD输出并提供DLF输出，并且其中在每个参考周期更新所述DLF输出。

17. 发明申请

US20080297239A1 OPTIMIZED GAIN FILTERING TECHNIQUE WITH NOISE SHAPING 有权
标题翻译：具有噪声形状优化的增益滤波技术
公开(公告)号：US20080297239A1
公开(公告)日：2008-12-04
申请号：US11755125
申请日：2007-05-30
申请人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
发明人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
IPC分类号： H03B1/04
CPC分类号： H03H11/10 , H03H11/1291 , H03H11/525
摘要： A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
摘要翻译：噪声整形和电压增益滤波三阶电路和方法包括至少一对输入电阻器; 位于所述至少一对输入电阻器之间的频率相关负电阻（FDNR）滤波器; 反馈电阻; 以及可操作地连接到所述反馈电阻器和所述至少一对输入电阻器的放大器，其中当电信号被引入所述电路时，所述FDNR滤波器适于在所述电信号之前将所述电信号中的信号阻挡器滤波到达用于信号放大的放大器，其中FDNR滤波器不对电信号的信噪比（SNR）贡献噪声，并且其中FDNR滤波器的传递函数的形状基本上是椭圆形的。

18. 发明申请

US20060226916A1 PLL lock management system 有权
标题翻译： PLL锁定管理系统
公开(公告)号：US20060226916A1
公开(公告)日：2006-10-12
申请号：US11103743
申请日：2005-04-11
申请人： Octavian Florescu , Amr Fahim , Chiewcharn Narathong
发明人： Octavian Florescu , Amr Fahim , Chiewcharn Narathong
IPC分类号： H03L7/00
CPC分类号： H03L7/199 , H03L7/0898 , H03L7/10
摘要： A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.
摘要翻译： PLL包括电荷泵，环路滤波器，VCO和校准单元。校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值不同的控制电压。校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化。

19. 发明授权

US07042972B2 Compact, low-power low-jitter digital phase-locked loop 有权
标题翻译：紧凑型低功耗低抖动数字锁相环
公开(公告)号：US07042972B2
公开(公告)日：2006-05-09
申请号：US10644490
申请日：2003-08-19
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： H03D3/24
CPC分类号： H03L7/10 , H03D13/004 , H03L7/085 , H03L7/093 , H03L7/0995 , H03L7/1075 , H03L2207/50
摘要： A digital PLL includes an adaptive PFD, an adaptive loop filter, an iDAC, an ICO, and a divider. The adaptive PFD receives a reference signal and a feedback signal, determines phase error between the two signals, and provides a PFD value for each phase comparison period. The magnitude of the PFD value is adjusted to achieve fast frequency acquisition and reduced jitter. The adaptive loop filter updates its output whenever a PFD value is received, widens the PLL loop bandwidth if a large phase error is detected, and narrows the loop bandwidth if a small average phase error is detected. The iDAC, which can be implemented with both steered and single-ended current sources, converts the loop filter output into analog current. The ICO provides an oscillator signal having a phase determined by the iDAC output. The divider divides the oscillator signal by a factor of N and provides the feedback signal.
摘要翻译：数字PLL包括自适应PFD，自适应环路滤波器，iDAC，ICO和分频器。自适应PFD接收参考信号和反馈信号，确定两个信号之间的相位误差，并为每个相位比较周期提供PFD值。调整PFD值的大小以实现快速频率采集和减少抖动。每当接收到PFD值时，自适应环路滤波器更新其输出，如果检测到大的相位误差，则会加宽PLL环路带宽，如果检测到小的平均相位误差，则会缩小环路带宽。可以使用转向和单端电流源实现的iDAC将环路滤波器输出转换为模拟电流。 ICO提供具有由iDAC输出确定的相位的振荡器信号。分频器将振荡器信号除以N的因子并提供反馈信号。

20. 发明授权

US06823033B2 &Sgr;&Dgr;delta modulator controlled phase locked loop with a noise shaped dither 失效
标题翻译： SigmaDeltadelta调制器控制的锁相环具有噪声形状的抖动
公开(公告)号：US06823033B2
公开(公告)日：2004-11-23
申请号：US10199758
申请日：2002-07-17
申请人： Amr Fahim
发明人： Amr Fahim
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： This disclosure is directed to a frequency synthesizer for use in a wireless communication device. The frequency synthesizer includes an oscillator, such as a voltage controlled oscillator (VCO) and a &Sgr;&Dgr;-controlled phase-locked loop (PLL) that determines and controls the of the output frequency of the frequency synthesizer. The &Sgr;&Dgr;-controlled PLL may implement a dithering signal generation technique that can reduce or eliminate the introduction of an average frequency offset.
摘要翻译：本公开涉及用于无线通信设备中的频率合成器。频率合成器包括诸如压控振荡器（VCO）和SigmaDelta控制的锁相环（PLL）的振荡器，其确定和控制频率合成器的输出频率。 SigmaDelta控制的PLL可以实现抖动信号生成技术，其可以减少或消除引入平均频率偏移。

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