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    • 1. 发明申请
    • METHOD AND APPARATUS FOR DC OFFSET CANCELLATION IN AMPLIFIERS
    • 放大器中DC偏移消除的方法和装置
    • US20080048773A1
    • 2008-02-28
    • US11466465
    • 2006-08-23
    • Amr FahimHassan ElwanAly Ismail
    • Amr FahimHassan ElwanAly Ismail
    • H03F1/02
    • H03F3/45475H03F3/45968H03F3/45977H03F2200/78H03F2203/45212H03F2203/45424H03F2203/45438H03F2203/45444H03F2203/45618
    • A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.
    • 在级联放大器中消除DC偏移误差的系统,电路和方法包括以任何级联和并联配置布置多个模拟电压和模拟电流放大器级; 在给定的放大器周围的反馈路径中可操作地连接反馈比较器和数字逻辑,其中数字逻辑包括实现包括固定切换和调制切换的自适应搜索算法的有限状态机; 可操作地连接放大器的差分输入端的开关以缩短放大器的两个输入端子; 对二进制加权元件执行固定切换,产生用于改变放大器输入处的DC偏移电压和电流中的任何一个的离散模拟步骤; 以及对用于改变DC偏移电压和电流中的任何一个的所有位的至少一个较低最低有效位(LSB)执行调制开关。
    • 4. 发明申请
    • OPERATIONAL AMPLIFIER CIRCUIT
    • 操作放大器电路
    • US20120182071A1
    • 2012-07-19
    • US13349861
    • 2012-01-13
    • Tatsuya Takei
    • Tatsuya Takei
    • H03F3/45
    • H03F3/45475H03F3/45192H03F3/4565H03F3/45937H03F2203/45082H03F2203/45406H03F2203/45444H03F2203/45482
    • An operational amplifier circuit may include a fully differential amplifier circuit that has a common mode feedback, the fully differential amplifier circuit performing operational amplification using a common mode base voltage as a center, a common mode detection circuit that detects a common mode output voltage of the fully differential amplifier circuit, a sample and hold circuit that performs sample and hold of an output of the common mode detection circuit, an operational circuit that detects a deviation between the output of the sample and hold circuit and a common mode reference voltage, the operational circuit outputting a voltage corresponding to the detected deviation and the common mode reference voltage, and a switching circuit that selects the common mode reference voltage or an output of the operational circuit to output the common mode reference voltage or the output as the common mode base voltage.
    • 运算放大器电路可以包括具有共模反馈的全差分放大器电路,全差分放大器电路使用共模基极电压作为中心进行运算放大,共模检测电路检测共模输出电压 全差分放大器电路,对共模检测电路的输出进行采样和保持的采样和保持电路,检测采样和保持电路的输出与共模参考电压之间的偏差的运算电路, 输出对应于检测到的偏差和共模参考电压的电压的电路,以及选择共模参考电压的开关电路或输出共模参考电压或输出作为共模基极电压的运算电路的输出 。
    • 7. 发明授权
    • Comparator circuit
    • 比较器电路
    • US08610465B2
    • 2013-12-17
    • US12993145
    • 2009-05-25
    • Christer Jansson
    • Christer Jansson
    • H03K5/22
    • H03F3/45753H03F2203/45292H03F2203/45444H03F2203/45538H03F2203/45634
    • A comparator circuit (5) comprising a fully differential main amplifier unit (10, 10b). The main amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit (10, 10b) and/or a bias current of a second branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first clock phase of the comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-capacitor accumulator unit with a differential input. The switched-capacitor accumulator unit is operatively connected to the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) for sampling voltages at the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) during the first clock phase, and operatively connected to the control port of the main amplifier unit (10, 10b) for supplying said one or more control voltages.
    • 一种包括全差分主放大器单元(10,10b)的比较器电路(5)。 主放大器单元(10,10b)包括控制端口,并且适于控制主放大器单元(10,10b)的第一支路的偏置电流和/或主放大器单元的第二支路的偏置电流 (10,10b),响应于提供给主放大器单元(10,10b)的控制端口的一个或多个控制电压。 比较器电路(5)包括用于在比较器电路(5)的第一时钟相位期间平衡主放大器单元(10,10b)的正和负输入端(12a,12b)处的电压的电路(60)。 此外,比较器电路(10,10a)包括具有差分输入的开关电容器累加器单元。 开关电容器蓄电单元可操作地连接到主放大器单元(10,10b)的正输出端和负输出端(14a,14b),用于对主放大器的正负输出端(14a,14b)采样电压 单元(10,10b),并且可操作地连接到主放大器单元(10,10b)的控制端口,用于提供所述一个或多个控制电压。