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1. 发明申请

US20090115458A1 CMOS COMPARATOR WITH HYSTERESIS 审中-公开
标题翻译：具有HYSTERESIS的CMOS比较器
公开(公告)号：US20090115458A1
公开(公告)日：2009-05-07
申请号：US11936125
申请日：2007-11-07
申请人： Frank Carr , Ahmed A. Emira
发明人： Frank Carr , Ahmed A. Emira
IPC分类号： H03K19/20 , H03K19/0948
CPC分类号： H03K3/3565
摘要： A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input voltage signal into an output voltage signal. An effective aspect ratio of the PMOS and NMOS transistors may be dependent on the level of the output voltage signal from the inverter. When a digital output of the inverter is “1”, the effective aspect ratio of the NMOS transistor is increased by turning on a second NMOS transistor, and a threshold voltage of the inverter is decreased.
摘要翻译：互补金属氧化物半导体（CMOS）比较器电路包括接收输入电压信号的多个p型金属氧化物半导体（PMOS）晶体管，多个n型金属氧化物半导体（NMOS）晶体管，可操作地连接到所述PMOS晶体管并且适于接收所述输入电压信号;以及逆变器，其适于将所述输入电压信号反转为输出电压信号。 PMOS和NMOS晶体管的有效长宽比可以取决于来自逆变器的输出电压信号的电平。当逆变器的数字输出为“1”时，通过接通第二NMOS晶体管来增加NMOS晶体管的有效长宽比，并且逆变器的阈值电压降低。

2. 发明申请

US20080297239A1 OPTIMIZED GAIN FILTERING TECHNIQUE WITH NOISE SHAPING 有权
标题翻译：具有噪声形状优化的增益滤波技术
公开(公告)号：US20080297239A1
公开(公告)日：2008-12-04
申请号：US11755125
申请日：2007-05-30
申请人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
发明人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
IPC分类号： H03B1/04
CPC分类号： H03H11/10 , H03H11/1291 , H03H11/525
摘要： A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
摘要翻译：噪声整形和电压增益滤波三阶电路和方法包括至少一对输入电阻器; 位于所述至少一对输入电阻器之间的频率相关负电阻（FDNR）滤波器; 反馈电阻; 以及可操作地连接到所述反馈电阻器和所述至少一对输入电阻器的放大器，其中当电信号被引入所述电路时，所述FDNR滤波器适于在所述电信号之前将所述电信号中的信号阻挡器滤波到达用于信号放大的放大器，其中FDNR滤波器不对电信号的信噪比（SNR）贡献噪声，并且其中FDNR滤波器的传递函数的形状基本上是椭圆形的。

3. 发明授权

US09349786B2 Fractal structures for fixed MEMS capacitors 有权
标题翻译：固定MEMS电容器的分形结构
公开(公告)号：US09349786B2
公开(公告)日：2016-05-24
申请号：US14239234
申请日：2012-08-17
申请人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
发明人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
IPC分类号： H01L21/02 , H01L49/02 , H01G5/18 , H01G5/16 , H01G7/00 , H01G13/00
CPC分类号： H01L28/40 , H01G5/16 , H01G5/18 , H01G7/00 , H01G13/00 , H01L28/86 , Y10T29/43
摘要： An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.
摘要翻译：分形固定电容器的实施例包括在微机电系统（MEMS）结构中的电容器体。电容器主体具有与具有分形形状的第二板分隔开与水平距离分形的第一板。第一板和第二板在同一平面内。这种分形固定电容器还包括基板，电容器本体位于该基板上。

4. 发明授权

US07592791B2 High efficiency DC-DC converter using pulse skipping modulation with programmable burst duration 有权
标题翻译：高效率DC-DC转换器采用具有可编程突发持续时间的脉冲跳跃调制
公开(公告)号：US07592791B2
公开(公告)日：2009-09-22
申请号：US11834950
申请日：2007-08-07
申请人： Ahmed A. Emira
发明人： Ahmed A. Emira
IPC分类号： G05F1/56
CPC分类号： H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： A DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration NTclk, where Tclk is the clock cycle interval. As the average load current increases, the time between bursts decreases so that average inductor current matches the load current. The burst duration is kept around NTclk by controlling the duty cycle of the output switches. The higher the load current, the higher is the duty cycle of the output switches. No current sensing is needed. The optimum burst duration for best efficiency curve is a function of the load capacitor.
摘要翻译：一种DC-DC转换器和使用具有可控脉冲串持续时间NTclk的脉冲跳跃调制（PSM）在低负载电流电平下提高DC-DC转换器的效率的方法，其中Tclk是时钟周期间隔。随着平均负载电流的增加，突发之间的时间减少，使得平均电感电流与负载电流匹配。突发持续时间通过控制输出开关的占空比保持在NTclk周围。负载电流越高，输出开关的占空比就越高。不需要电流检测。最佳效率曲线的最佳突发持续时间是负载电容的函数。

5. 发明授权

US09306450B2 High voltage charge pump 有权
标题翻译：高压电荷泵
公开(公告)号：US09306450B2
公开(公告)日：2016-04-05
申请号：US14239335
申请日：2012-08-24
申请人： Ahmed A. Emira , Mohamed Abdelghany , Mohannad Yomn Elsayed , Amro M. Elshurafa , Khaled Nabil Salama
发明人： Ahmed A. Emira , Mohamed Abdelghany , Mohannad Yomn Elsayed , Amro M. Elshurafa , Khaled Nabil Salama
IPC分类号： G05F1/10 , H02M3/07
CPC分类号： H02M3/07 , H02M3/073
摘要： Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.
摘要翻译：描述高压电荷泵的各种实施例。一个实施例是一种电荷泵电路，其包括多个开关级，每个开关级包括时钟输入，时钟输入反相，时钟输出和时钟输出反相。电路还包括多个泵浦电容器，其中一个或多个泵浦电容器耦合到相应的开关级。所述电路还包括耦合到所述多个开关级之间的最后切换级的最大选择电路，所述最大选择电路被配置为滤波所述输出时钟上的噪声和所述最后切换级的所述输出时钟反相，所述最大选择电路还被配置以产生基于最后切换级的输出时钟和输出时钟反相的DC输出电压。

6. 发明授权

US07728550B2 Integrated CMOS DC-DC converter implementation in low-voltage CMOS technology using LDO regulator 有权
标题翻译：集成CMOS DC-DC转换器在低压CMOS技术中采用LDO稳压器
公开(公告)号：US07728550B2
公开(公告)日：2010-06-01
申请号：US11780539
申请日：2007-07-20
申请人： Frank Carr , Ahmed A. Emira , Hassan Elwan
发明人： Frank Carr , Ahmed A. Emira , Hassan Elwan
IPC分类号： H01M10/46
CPC分类号： H02M3/156 , H02M2001/0045 , H02M2001/007
摘要： An electrical circuit and method of power management of a cellular telephone includes a battery adapted to produce a battery voltage; a LDO regulator operatively connected to the battery and adapted to provide a constant supply voltage from the battery voltage; and a DC-DC converter operatively connected to the LDO regulator, wherein the DC-DC converter is adapted to step down the constant supply voltage to a lower voltage level, wherein the LDO regulator and the DC-DC converter are embedded on a single integrated circuit chip. The constant supply voltage equals 3.6V at an output of the LDO, and the constant supply voltage is applied to an input of the DC-DC converter. Moreover, the battery voltage equals at most 5.5V.
摘要翻译：蜂窝电话的电路和电源管理方法包括适于产生电池电压的电池; LDO调节器可操作地连接到电池并且适于从电池电压提供恒定的电源电压; 以及可操作地连接到所述LDO调节器的DC-DC转换器，其中所述DC-DC转换器适于将所述恒定电源电压降低到较低电压电平，其中所述LDO调节器和所述DC-DC转换器嵌入在单个集成电路芯片。在LDO的输出端，恒定电源电压等于3.6V，恒定的电源电压被施加到DC-DC转换器的输入端。此外，电池电压等于5.5V以下。

7. 发明授权

US07592863B2 Optimized gain filtering technique with noise shaping 有权
标题翻译：具有噪声整形的优化增益滤波技术
公开(公告)号：US07592863B2
公开(公告)日：2009-09-22
申请号：US11755125
申请日：2007-05-30
申请人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
发明人： Hassan Elwan , Amr Fahim , Edward Youssounan , Ahmed A. Emira , Dejun Wang
IPC分类号： H03K5/00
CPC分类号： H03H11/10 , H03H11/1291 , H03H11/525
摘要： A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.
摘要翻译：噪声整形和电压增益滤波三阶电路和方法包括至少一对输入电阻器; 位于所述至少一对输入电阻器之间的频率相关负电阻（FDNR）滤波器; 反馈电阻; 以及可操作地连接到所述反馈电阻器和所述至少一对输入电阻器的放大器，其中当电信号被引入所述电路时，所述FDNR滤波器适于在所述电信号之前将所述电信号中的信号阻挡器滤波到达用于信号放大的放大器，其中FDNR滤波器不对电信号的信噪比（SNR）贡献噪声，并且其中FDNR滤波器的传递函数的形状基本上是椭圆形的。

8. 发明申请

US20090021228A1 INTEGRATED CMOS DC-DC CONVERTER IMPLEMENTATION IN LOW-VOLTAGE CMOS TECHNOLOGY USING LDO REGULATOR 有权
标题翻译：低压CMOS技术中使用LDO稳压器的集成CMOS DC-DC转换器实现
公开(公告)号：US20090021228A1
公开(公告)日：2009-01-22
申请号：US11780539
申请日：2007-07-20
申请人： Frank Carr , Ahmed A. Emira , Hassan Elwan
发明人： Frank Carr , Ahmed A. Emira , Hassan Elwan
IPC分类号： G05F1/563
CPC分类号： H02M3/156 , H02M2001/0045 , H02M2001/007
摘要： An electrical circuit and method of power management of a cellular telephone includes a battery adapted to produce a battery voltage; a LDO regulator operatively connected to the battery and adapted to provide a constant supply voltage from the battery voltage; and a DC-DC converter operatively connected to the LDO regulator, wherein the DC-DC converter is adapted to step down the constant supply voltage to a lower voltage level, wherein the LDO regulator and the DC-DC converter are embedded on a single integrated circuit chip. The constant supply voltage equals 3.6V at an output of the LDO, and the constant supply voltage is applied to an input of the DC-DC converter. Moreover, the battery voltage equals at most 5.5V.
摘要翻译：蜂窝电话的电路和电源管理方法包括适于产生电池电压的电池; LDO调节器可操作地连接到电池并且适于从电池电压提供恒定的电源电压; 以及可操作地连接到所述LDO调节器的DC-DC转换器，其中所述DC-DC转换器适于将所述恒定电源电压降低到较低电压电平，其中所述LDO调节器和所述DC-DC转换器嵌入在单个集成电路芯片。在LDO的输出端，恒定电源电压等于3.6V，恒定的电源电压被施加到DC-DC转换器的输入端。此外，电池电压等于5.5V以下。

9. 发明授权

US09614024B2 Fractal structures for MEMS variable capacitors 有权
公开(公告)号：US09614024B2
公开(公告)日：2017-04-04
申请号：US14239346
申请日：2012-08-21
申请人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
发明人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
IPC分类号： H01G5/00 , H01G7/00 , H01L49/02 , H01G5/18 , H01G5/16 , H01G13/00
CPC分类号： H01L28/40 , H01G5/16 , H01G5/18 , H01G7/00 , H01G13/00 , H01L28/86 , Y10T29/43
摘要： In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

10. 发明申请

US20090046487A1 HIGH EFFICIENCY DC-DC CONVERTER USING PULSE SKIPPING MODULATION WITH PROGRAMMABLE BURST DURATION 有权
标题翻译：高效率DC-DC转换器，使用脉冲滑移调制与可编程的脉冲时间
公开(公告)号：US20090046487A1
公开(公告)日：2009-02-19
申请号：US11834950
申请日：2007-08-07
申请人： Ahmed A. Emira
发明人： Ahmed A. Emira
IPC分类号： H02M3/157
CPC分类号： H02M3/158 , H02M2001/0032 , Y02B70/16
摘要： A DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration NTclk, where Tclk is the clock cycle interval. As the average load current increases, the time between bursts decreases so that average inductor current matches the load current. The burst duration is kept around NTclk by controlling the duty cycle of the output switches. The higher the load current, the higher is the duty cycle of the output switches. No current sensing is needed. The optimum burst duration for best efficiency curve is a function of the load capacitor.
摘要翻译：一种DC-DC转换器和使用具有可控脉冲串持续时间NTclk的脉冲跳跃调制（PSM）在低负载电流电平下提高DC-DC转换器的效率的方法，其中Tclk是时钟周期间隔。随着平均负载电流的增加，突发之间的时间减少，使得平均电感电流与负载电流匹配。突发持续时间通过控制输出开关的占空比保持在NTclk周围。负载电流越高，输出开关的占空比就越高。不需要电流检测。最佳效率曲线的最佳突发持续时间是负载电容的函数。

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