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11. 发明授权

US4769744A Semiconductor chip packages having solder layers of enhanced durability 失效
标题翻译：具有提高耐久性的焊料层的半导体芯片封装
公开(公告)号：US4769744A
公开(公告)日：1988-09-06
申请号：US851275
申请日：1986-04-10
申请人： Constantine A. Neugebauer , Richard O. Carlson
发明人： Constantine A. Neugebauer , Richard O. Carlson
IPC分类号： H01L23/32 , H01L23/48 , H05K7/20
CPC分类号： H01L24/06 , H01L23/32 , H01L24/72 , H01L2224/05554 , H01L2224/48091 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15173 , H01L2924/16152 , H01L2924/351
摘要： Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it fails due to increased thermal resistance arising from structural degradation of the solder layers.
摘要翻译：半导体芯片封装中的用于电连接到半导体芯片上的电极的导电的导体的焊料层受到超过约2磅/平方英寸的横向压缩力。由于由于焊料层的结构劣化引起的耐热性增加，因此半导体芯片封装在其失效之前的加热和冷却循环次数显着增加。

12. 发明授权

US4750666A Method of fabricating gold bumps on IC's and power chips 失效
标题翻译：在IC和功率芯片上制造金凸块的方法
公开(公告)号：US4750666A
公开(公告)日：1988-06-14
申请号：US853255
申请日：1986-04-17
申请人： Constantine A. Neugebauer , James A. Loughran
发明人： Constantine A. Neugebauer , James A. Loughran
IPC分类号： B23K20/00 , H01L21/00 , H01L23/485 , B23K31/02
CPC分类号： H01L24/13 , B23K20/007 , H01L24/11 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/05669 , H01L2224/13099 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48669 , H01L2224/48724 , H01L2224/48744 , H01L2224/48769 , H01L2224/78301 , H01L2224/85201 , H01L2224/85205 , H01L24/45 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01024 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/14
摘要： A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.
摘要翻译：用于在半导体芯片的金属化焊盘上沉积金凸块的方法使用市售的热压或热镍金线焊接机。该方法包括以下步骤：在金属化焊盘上沉积附有金属线的金球，并且去除金属丝，使得焊盘上留下金凸块。

13. 发明授权

US5366906A Wafer level integration and testing 失效
标题翻译：晶圆级集成和测试
公开(公告)号：US5366906A
公开(公告)日：1994-11-22
申请号：US962000
申请日：1992-10-16
申请人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
发明人： Robert J. Wojnarowski , Constantine A. Neugebauer , Wolfgang Daum , Bernard Gorowitz , Eric J. Wildi , Michael Gdula , Stanton E. Weaver, Jr. , Anthony A. Immorlica, Jr.
IPC分类号： G01R31/3185 , H01L21/301 , H01L21/66 , H01L23/538 , H01L23/58 , G01R31/26
CPC分类号： H01L22/22 , H01L22/32 , H01L23/5389 , H01L24/24 , H01L24/82 , G01R31/318505 , G01R31/318533 , H01L2224/2402 , H01L2224/24137 , H01L2224/24227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/351
摘要： In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.
摘要翻译：在制造晶片级集成互连件时，使用临时或永久的电介质层和电导体图案来提供晶片级整合或测试和老化。可以使用抗蚀剂来覆盖晶片上的IC焊盘的区域，而去除电导体图案的其余部分以提供晶片级整合结构的修复。电导体的图案可以被配置为使得在多个晶片上的至少一些子电路之间的导体长度对于信号传播目的而基本上是电相等的; 可以使用粘合剂将另外的晶片层压到晶片上; 受控的曲折可以被切入晶片; 并且晶片可以互连到接口环。

14. 发明授权

US5304847A Direct thermocompression bonding for thin electronic power chips 失效
标题翻译：用于薄电子功率芯片的直接热压接
公开(公告)号：US5304847A
公开(公告)日：1994-04-19
申请号：US7300
申请日：1993-01-21
申请人： Constantine A. Neugebauer , Homer H. Glascock, II , Kyung W. Paik , James G. McMullen
发明人： Constantine A. Neugebauer , Homer H. Glascock, II , Kyung W. Paik , James G. McMullen
IPC分类号： H01L21/60 , H01L21/603 , H01L23/482 , H01L23/48 , H01L29/40
CPC分类号： H01L24/80 , H01L23/4827 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1301 , H01L2924/14 , H01L2924/30107
摘要： Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.
摘要翻译：退火铜箔（12）涂覆有铬膜（16），然后用适当厚度的金膜（14）涂覆，并且热压粘合到硅芯片（30）上的铝金属化基板（18）上以提供可焊接，高电流接触芯片。箔形成适当的电网接触图案（40），并且仅在芯片上存在铝金属化的情况下结合到硅芯片。箔的翼（翼）部分（46）延伸超过硅芯片的边界，用于随后在箔上的后向反射以在预先指定的位置（49）提供电接触。通过穿过位于箔区域正上方的陶瓷盖制成与箔的外部接触。因此，主要铜箔与铝半导体焊盘的直接热压接可以通过金属间AuAl2连接和铝层将铜导体固定在硅芯片上来取代当前的金制定位/凸点连接。

15. 发明授权

US5184206A Direct thermocompression bonding for thin electronic power chips 失效
标题翻译：直接热电偶连接电子电源
公开(公告)号：US5184206A
公开(公告)日：1993-02-02
申请号：US603495
申请日：1990-10-26
申请人： Constantine A. Neugebauer , Homer H. Glascock, II , Kyung W. Paik , James G. McMullen , Martha M. Neugebauer
发明人： Constantine A. Neugebauer , Homer H. Glascock, II , Kyung W. Paik , James G. McMullen , Martha M. Neugebauer
IPC分类号： H01L21/60 , H01L21/603 , H01L23/482
CPC分类号： H01L24/80 , H01L23/4827 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1301 , H01L2924/14 , H01L2924/30107
摘要： Annealed copper foil (12) is coated with chromium film (16), followed by coating with an appropriate thickness of gold film (14) and is thermocompression bonded to an aluminum metallized substrate (18) on a silicon chip (30) to provide solderable, high current contacts to the chip. The foil is formed into appropriate electrical network-contact patterns (40) and is bonded to the silicon chip only where aluminum metallization exists on the chip. Leaf (wing) portions (46) of the foil extend beyond the boundaries of the silicon chip for subsequent retroflexing over the foil to provide electrical contact at predesignated locations (49). External contacts to the foil are made by penetrating through a ceramic lid positioned directly above the foil area. Thus, direct thermocompression bonding of a principally copper foil to aluminum semiconductor pads can replace current gold detent/bump connections by securing a copper conductor to a silicon chip through an intermetallic AuAl.sub.2 link and an aluminum stratum.
摘要翻译：退火铜箔（12）涂覆有铬膜（16），然后用适当厚度的金膜（14）涂覆，并且热压粘合到硅芯片（30）上的铝金属化基板（18）上以提供可焊接，高电流接触芯片。箔形成适当的电网接触图案（40），并且仅在芯片上存在铝金属化的情况下结合到硅芯片。箔的翼（翼）部分（46）延伸超过硅芯片的边界，用于随后在箔上的后向反射以在预先指定的位置（49）提供电接触。通过穿过位于箔区域正上方的陶瓷盖制成与箔的外部接触。因此，主要铜箔与铝半导体焊盘的直接热压接可以通过金属间AuAl2连接和铝层将铜导体固定在硅芯片上来取代当前的金制定位/凸点连接。

16. 发明授权

US5018002A High current hermetic package including an internal foil and having a lead extending through the package lid and a packaged semiconductor chip 失效
标题翻译：高电流密封包装，包括内部箔片，并且具有延伸穿过封装盖的引线和封装的半导体芯片
公开(公告)号：US5018002A
公开(公告)日：1991-05-21
申请号：US375641
申请日：1989-07-03
申请人： Constantine A. Neugebauer , Wolfgang Daum
发明人： Constantine A. Neugebauer , Wolfgang Daum
IPC分类号： H01L23/049 , H01L23/482 , H01L23/485
CPC分类号： H01L24/10 , H01L23/049 , H01L23/482 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1306 , H01L2924/14 , H01L2924/15787 , H01L2924/30107
摘要： A hermetic semiconductor chip package includes a conductive foil bonded to a contact pad of the chip and connected to an external lead of the package through an aperture in the insulating material of the package lid.
摘要翻译：密封半导体芯片封装包括接合到芯片的接触焊盘并通过封装盖的绝缘材料中的孔连接到封装的外部引线的导电箔。

17. 发明授权

US4901136A Multi-chip interconnection package 失效
标题翻译：多芯片互连包
公开(公告)号：US4901136A
公开(公告)日：1990-02-13
申请号：US285363
申请日：1988-12-15
申请人： Constantine A. Neugebauer , Lionel M. Levinson , Homer H. Glascock, II , Charles W. Eichelberger , Robert J. Wojnarowski , Richard O. Carlson
发明人： Constantine A. Neugebauer , Lionel M. Levinson , Homer H. Glascock, II , Charles W. Eichelberger , Robert J. Wojnarowski , Richard O. Carlson
IPC分类号： H01L23/04 , H01L23/495 , H01L23/538 , H01L25/065
CPC分类号： H01L23/5383 , H01L23/04 , H01L23/49541 , H01L23/5389 , H01L25/0655 , H01L2924/0002 , H01L2924/01079
摘要： A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.
摘要翻译：一种用于将多个集成电路芯片互连到功能单元的封装，该功能单元包括具有接地和功率传导层的多层基板和用于将其端子焊盘保持在与基板相对的一侧的端子焊盘的框架。芯片上的电源和接地端子焊盘通过记录穿过框架并进入衬底的导电馈通件与基板中适当的电源或导电层接触而耦合到适当的电位。芯片上的信号焊盘通过位于与衬底相对的框架侧上的芯片上方的导电层相互连接。

18. 发明授权

US5418002A Direct bonding of copper to aluminum nitride substrates 失效
标题翻译：铜直接键合到氮化铝衬底
公开(公告)号：US5418002A
公开(公告)日：1995-05-23
申请号：US632876
申请日：1990-12-24
申请人： Kyung W. Paik , Constantine A. Neugebauer
发明人： Kyung W. Paik , Constantine A. Neugebauer
IPC分类号： B32B9/00 , B32B15/04 , C04B35/581 , C04B37/02 , C04B41/00 , C04B41/80 , H05K1/03 , H05K3/02 , H05K3/38 , B05D5/12
CPC分类号： H01S5/02 , C04B37/021 , C04B37/025 , C04B41/0036 , C04B41/80 , C04B2235/6562 , C04B2235/6565 , C04B2235/6586 , C04B2235/6588 , C04B2237/06 , C04B2237/366 , C04B2237/407 , C04B2237/704 , C04B2237/708 , H05K1/0306 , H05K3/022 , H05K3/38
摘要： A process for direct bonding a copper film to an yttria-doped aluminum nitride substrate comprises treating the substrate by preoxidation at elevated temperature to create an overlying thin film of Al.sub.2 O.sub.3, followed by step cooling to a lower temperature. A copper foil of thickness between 1.0 and 4.0 microns and generally perforated or otherwise foraminous, is eutectically direct bonded to the substrate by the known direct bond copper (DBC) process. The resultant article exhibits high thermal conductivity, low permittivity and high mechanical strength. The peel strength of the copper film on the AlN substrate exceeds the peel strengths previously attainable in the industry.
摘要翻译：用于将铜膜直接结合到掺杂氧化钇的氮化铝衬底的方法包括通过在升高的温度下预氧化来处理衬底，以产生上覆的Al 2 O 3薄膜，然后逐步冷却至较低温度。通过已知的直接键合铜（DBC）工艺将厚度在1.0和4.0微米之间，通常穿孔或以其它方式存在的铜箔共晶地直接结合到衬底上。所得物品具有高导热性，低介电常数和高机械强度。 AlN衬底上的铜膜的剥离强度超过了以前在工业上可获得的剥离强度。

19. 发明授权

US5291066A Moisture-proof electrical circuit high density interconnect module and method for making same 失效
标题翻译：防潮电路高密度互连模块及其制造方法
公开(公告)号：US5291066A
公开(公告)日：1994-03-01
申请号：US791690
申请日：1991-11-14
申请人： Constantine A. Neugebauer , Herbert S. Cole , Eugene L. Bartels , Raymond A. Fillion
发明人： Constantine A. Neugebauer , Herbert S. Cole , Eugene L. Bartels , Raymond A. Fillion
IPC分类号： H01L23/00 , H01L23/10 , H01L23/538 , H01L23/02
CPC分类号： H01L23/564 , H01L23/10 , H01L23/538 , H01L23/5383 , H01L23/5384 , H01L24/24 , H01L24/82 , H01L2224/24227 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041
摘要： A moisture-proof integrated circuit module includes at least one integrated circuit component in a high density interconnect (HDI) structure fabricated by applying to a substrate successive multiple ply sequences having a plurality of via holes therein. The sequences overlie the component(s) and the module substrate, and each sequence includes a dielectric film and a plurality of lands comprised of metal that extends into the vias of the sequence to provide electrical interconnections. The module includes at least one moisture barrier film to prevent penetration of moisture through the module to the circuit component(s).
摘要翻译：一种防潮集成电路模块包括至少一个集成电路部件，该集成电路部件是通过在其中连续施加多个通孔的衬底施加到衬底上而制造的高密度互连（HDI）结构。序列覆盖在组件和模块衬底上，并且每个序列包括介电膜和由金属组成的多个焊盘，其延伸到序列的通孔中以提供电互连。模块包括至少一个防潮膜，以防止湿气穿过模块穿过电路部件。

20. 发明授权

US4816422A Fabrication of large power semiconductor composite by wafer interconnection of individual devices 失效
标题翻译：通过单个器件的晶片互连制造大功率半导体复合材料
公开(公告)号：US4816422A
公开(公告)日：1989-03-28
申请号：US947151
申请日：1986-12-29
申请人： Alexander J. Yerman , Constantine A. Neugebauer
发明人： Alexander J. Yerman , Constantine A. Neugebauer
IPC分类号： H01L21/66 , H01L23/528 , H01L23/538 , H01L7/00
CPC分类号： H01L22/22 , H01L23/528 , H01L23/5385 , H01L2924/0002 , Y10S148/093 , Y10S148/162
摘要： A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.
摘要翻译：从形成在公共半导体晶片上的多个基本相同的单个半导体器件制造复合半导体的方法包括测试晶片上的器件以产生可接受和不可接受器件的位置映射，将晶片分成多个区域通过共同的导电路径将一个给定区域内的可接受的设备上的对应的接触焊盘连接在一起，该导电通路支撑在覆盖焊盘的电介质膜上，该膜具有适当定位的孔，填充有导电材料，导电路径和仅接受的设备的底层接触垫。给定区域内的装置以形成操作阵列的方式相互配合; 单个或多个阵列可以耦合在一起以形成具有共同的外部触点和散热器支撑件的复合封装。

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