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11. 发明授权

US06448608B1 Capping layer 有权
标题翻译：封盖层
公开(公告)号：US06448608B1
公开(公告)日：2002-09-10
申请号：US09631894
申请日：2000-08-04
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer, and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer, and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current leakage between the tungsten plug and the stacks.
摘要翻译：一种改进的闪速存储器件，其包括用氧化物层，保护层和绝缘层保护的芯堆叠和外围堆叠。使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种不同的引线引起的芯堆叠和外围堆叠的损坏在制造闪速存储器件期间蚀刻并提供绝缘以减少钨丝塞和叠层之间的不必要的电流泄漏。

12. 发明授权

US06969654B1 Flash NVROM devices with UV charge immunity 有权
标题翻译：具有UV电荷免疫功能的闪存NVROM器件
公开(公告)号：US06969654B1
公开(公告)日：2005-11-29
申请号：US09727714
申请日：2000-11-28
申请人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
发明人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L23/552 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28273 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.
摘要翻译：一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

13. 发明授权

US06635943B1 Method and system for reducing charge gain and charge loss in interlayer dielectric formation 有权
标题翻译：降低层间电介质形成中电荷增益和电荷损失的方法和系统
公开(公告)号：US06635943B1
公开(公告)日：2003-10-21
申请号：US09533617
申请日：2000-03-22
申请人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
发明人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
IPC分类号： H01L2900
CPC分类号： H01L21/823425 , H01L21/76819 , H01L21/76837
摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.
摘要翻译：公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。该方法和系统包括在下层上提供层间电介质。层间电介质能够间隙填充，同时仅使用相对较低迁移率的物质。该方法和系统还包括平坦化层间电介质的表面。

14. 发明授权

US06548334B1 Capping layer 失效
标题翻译：封盖层
公开(公告)号：US06548334B1
公开(公告)日：2003-04-15
申请号：US10179061
申请日：2002-06-24
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L21337
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current between the tungsten plug and the stacks.
摘要翻译：一种制造具有由氧化层，保护层和绝缘层保护的芯堆叠和外围堆叠的改进的闪存器件的方法。使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种蚀刻引起的芯堆叠和外围堆叠的损坏在制造闪速存储器件期间提供绝缘以减少钨插头和堆叠之间的不必要的电流。

15. 发明授权

US06653190B1 Flash memory with controlled wordline width 失效
标题翻译：具有受控字线宽度的闪存
公开(公告)号：US06653190B1
公开(公告)日：2003-11-25
申请号：US10023436
申请日：2001-12-15
申请人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
发明人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。使用光掩模处理硬掩模材料以形成硬掩模。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

16. 发明授权

US6136649A Method for removing anti-reflective coating layer using plasma etch process after contact CMP 有权
标题翻译：接触CMP后使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US6136649A
公开(公告)日：2000-10-24
申请号：US416389
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L21/311 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/31116 , H01L29/66825
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH.sub.3 F)/oxygen (O.sub.2) etch chemistry is used to selectively remove the ARC layer. The CH.sub.3 F/O.sub.2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer or the tungsten contacts.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层。 CH3F / O2蚀刻化学蚀刻ARC层的速度明显快于介电层或钨触点的蚀刻速率。

17. 发明授权

US07157335B1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices 有权
标题翻译：单独使用BPTEOS ILD或BPTEOS ILD的薄的未掺杂TEOS来改善多位存储器件中的电荷损耗和接触电阻
公开(公告)号：US07157335B1
公开(公告)日：2007-01-02
申请号：US10917562
申请日：2004-08-13
申请人： Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Lu You , Angela T. Hui , Yi He , Brian Mooney , Jean Yei-Mei Yang , Mark T. Ramsbey
发明人： Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Lu You , Angela T. Hui , Yi He , Brian Mooney , Jean Yei-Mei Yang , Mark T. Ramsbey
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

18. 发明授权

US07018896B2 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing 有权
标题翻译：紫外线阻挡层，用于在BEOL处理中减少SONOS双位闪存器件的紫外线充电
公开(公告)号：US07018896B2
公开(公告)日：2006-03-28
申请号：US10818112
申请日：2004-04-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L21/00
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括接触帽层或基本上不透紫外线的接触覆盖层的基本不透紫外不透明的子层。

19. 发明授权

US06589841B1 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate 失效
公开(公告)号：US06589841B1
公开(公告)日：2003-07-08
申请号：US10180772
申请日：2002-06-25
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

20. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

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