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11. 发明授权

US5990704A Internal drive circuit providing third input pin state 失效
标题翻译：内部驱动电路提供第三输入引脚状态
公开(公告)号：US5990704A
公开(公告)日：1999-11-23
申请号：US942858
申请日：1997-10-02
申请人： Charles R. Erickson , Brian D. Erickson
发明人： Charles R. Erickson , Brian D. Erickson
IPC分类号： H03K19/0175 , H03K19/20
CPC分类号： H03K19/0002 , H03K19/173
摘要： A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.
摘要翻译：提供多状态输入驱动结构以转发外部产生的高和低输入信号，以及接收至少第三，内部产生的相对较弱的信号，优选振荡信号，其触发第三内部转发信号，当两者接收高低输入信号。本发明的电路驱动来自单个外部信号源的三个内部转发的输出信号。由于对于两个周期延迟不影响性能的设备上的每个引脚可能会复制此电路，所以N个输入上的第三个输入状态的可用性允许3N输入代码，而不是常规的“高”和“低”电平的2N 通常可用。

12. 发明授权

US5923614A Structure and method for reading blocks of data from selectable points in a memory device 失效
标题翻译：用于从存储器件中的可选点读取数据块的结构和方法
公开(公告)号：US5923614A
公开(公告)日：1999-07-13
申请号：US71144
申请日：1998-04-30
申请人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
发明人： Charles R. Erickson , Robert O. Conn , Lois D. Cartier
IPC分类号： G11C8/04 , H03K19/177 , G11C8/00 , G06F7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
摘要翻译：提供了自寻址存储器件，其可以从设备中的多于一个初始位置开始提供数据块，并且可以具有在任一方向上读取的选项。该存储设备可以有效地存储用于配置一个或多个可配置逻辑设备的多个可能具有不同大小的比特流。可以以任何顺序访问每个存储的比特流。在一个实施例中，可配置逻辑器件是现场可编程门阵列（“FPGA”）。在一个实施例中，存储器件是从全零读取或从全部读取的只读存储器（“ROM”）。在一个实施例中，ROM包括允许级联多个ROM的双向芯片使能链。

13. 发明授权

US5592105A Configuration logic to eliminate signal contention during reconfiguration 失效
标题翻译：在配置过程中消除信号争用的配置逻辑
公开(公告)号：US5592105A
公开(公告)日：1997-01-07
申请号：US375763
申请日：1995-01-20
申请人： Edmond Y. Cheung , Charles R. Erickson
发明人： Edmond Y. Cheung , Charles R. Erickson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177 , G11C19/00 , G11C19/28
CPC分类号： G06F17/5054 , H03K19/1737 , H03K19/17748 , H03K19/1776 , H03K19/17772
摘要： A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.
摘要翻译：一种在可编程逻辑器件的重新配置期间消除信号争用的方法包括以下步骤：将多个存储器单元布置成集合并且选择性地对存储单元进行编程，所述存储器单元在一个时间上在第一方向或第二方向上编程。用于提供选择性编程的结构包括多个同步触发器和多个相关联的双输入多路复用器。提供给多路复用器的第一逻辑状态的控制信号提供通过触发器的第一信号传播方向，而处于第二逻辑状态的控制信号通过触发器提供第二信号传播方向。

14. 发明授权

US5581199A Interconnect architecture for field programmable gate array using variable length conductors 失效
标题翻译：使用可变长度导体的现场可编程门阵列的互连架构
公开(公告)号：US5581199A
公开(公告)日：1996-12-03
申请号：US368692
申请日：1995-01-04
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

15. 发明授权

US4106090A Monolithic microcomputer central processor 失效
标题翻译：单片微机中央处理器
公开(公告)号：US4106090A
公开(公告)日：1978-08-08
申请号：US760063
申请日：1977-01-17
申请人： Charles R. Erickson , Hemraj K. Hingarh , Robert Moeckel , Dan Wilnai
发明人： Charles R. Erickson , Hemraj K. Hingarh , Robert Moeckel , Dan Wilnai
IPC分类号： G06F9/38 , G06F15/78 , G06F7/48
CPC分类号： G06F15/7864
摘要： A central processing unit (CPU) is utilized in combination with external memories and input/output devices to form a Microcomputer System. The CPU is a 16-bit fixed word length processor monolithically integrated onto a single semiconductor chip which uses two's complement arithmetic for computations. The CPU includes an arithmetic logic unit (ALU), accumulators, data path multiplexers, program counter means, and programmable logic arrays to control operation of the processor.The processor of this invention is capable of using a homogeneous memory, wherein instructions and data are both stored in the same memory. In the disclosed embodiment, 15 of the 16-bits are used for addressing the memory. Thus, the processor is capable of directly addressing 32,768 16-bit words in the memory.An external 16-bit bus is used to interconnect the external memory and input/output devices with the CPU. Bidirectional three-state logic is used to enable both input and output data, as well as memory addresses, to be transmitted over the same bus thereby simplifying design. In addition, provision is made for coupling an operator console into a system formed around the processor of this invention, thus allowing for a user to interface with the system.
摘要翻译：中央处理单元（CPU）与外部存储器和输入/输出设备结合使用以形成微计算机系统。 CPU是一个16位固定字长处理器，单片集成到单个半导体芯片上，采用二进制补码运算进行计算。 CPU包括算术逻辑单元（ALU），累加器，数据路径多路复用器，程序计数器装置和可编程逻辑阵列，以控制处理器的操作。

16. 发明授权

US6057704A Partially reconfigurable FPGA and method of operating same 失效
标题翻译：部分可重新配置FPGA及其操作方法
公开(公告)号：US6057704A
公开(公告)日：2000-05-02
申请号：US990154
申请日：1997-12-12
申请人： Bernard J. New , Charles R. Erickson
发明人： Bernard J. New , Charles R. Erickson
IPC分类号： H03K19/177 , G06F7/38 , G11C8/00 , G11C16/04
CPC分类号： H03K19/17756 , H03K19/17704
摘要： A field programmable gate array (FPGA) having an array of configuration memory cells arranged in rows and columns. The configuration memory cells store configuration data values for configuring the FPGA. Each configuration memory cell is coupled to a corresponding row line through a corresponding cell access transistor. A row access circuit is coupled to the row lines. To re-program a first set (but not a second set) of configuration memory cells in a column, the row access circuit initially pre-charges each of the row lines, and then provides configuration data values on a first set (but not a second set) of the row lines. All cell access transistors in the column are coupled to a column select line. To avoid losing data in any memory cell, a relatively low read voltage, followed by a higher write voltage, is applied to the column select line. When the read voltage is applied to the column select line, the associated cell access transistors are weakly turned on. As a result, the row lines are charged to states which correspond to the configuration data values stored by the configuration memory cells. Consequently, when the write voltage is subsequently applied to the column select line, configuration data values stored by the second set of configuration memory cells are not disturbed.
摘要翻译：具有排列成行和列的配置存储单元阵列的现场可编程门阵列（FPGA）。配置存储单元存储用于配置FPGA的配置数据值。每个配置存储单元通过相应的单元存取晶体管耦合到相应的行线。行访问电路耦合到行线。为了重新编程列中的配置存储器单元的第一组（但不是第二组），行访问电路首先预先对每行行进行预充电，然后在第一组（但不是第一组）上提供配置数据值第二组）行行。列中的所有单元存取晶体管耦合到列选择线。为了避免在任何存储单元中丢失数据，将相对较低的读取电压（随后较高的写入电压）施加到列选择线。当读取电压被施加到列选择线时，相关联的单元存取晶体管弱导通。结果，行线被充电到对应于由配置存储器单元存储的配置数据值的状态。因此，当写入电压随后被施加到列选择线时，由第二组配置存储单元存储的配置数据值不被干扰。

17. 发明授权

US5969543A Input signal interface with independently controllable pull-up and pull-down circuitry 失效
标题翻译：输入信号接口，具有独立可控的上拉和下拉电路
公开(公告)号：US5969543A
公开(公告)日：1999-10-19
申请号：US790873
申请日：1997-02-03
申请人： Charles R. Erickson , Peter H. Alfke
发明人： Charles R. Erickson , Peter H. Alfke
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585
摘要： An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins. The input interface contains two multiplexers which drive the pull-up and pull-down devices, each multiplexer being coupled to receive inputs from programmable memory cells and having a common control line.
摘要翻译：一种用于逻辑器件的输入接口电路，其具有上拉和下拉器件的配置，用于基于未驱动的输入信号定义逻辑电平，其中上拉和下拉器件是独立且可单独编程的以跟随输入信号（例如，保持器电路），或者跟随输入信号的倒数，或永久地编程或永久地编程。接口电路可用于为不具有已知驱动源的IC输入（或内部线路）提供已知且可编程的输出信号。通过允许这种程度的灵活性，本发明的输入接口电路在编程控制下，基于输入信号产生具有正或负反馈的输出信号; 或者输入接口电路提供恒定的高或恒定的低信号输出，或者可以作为输出振荡或提供高阻抗响应。在输入引脚（或内部线路）不被总线或源驱动器驱动的情况下，输入接口提供多个用于提供预定输出的灵活配置。在可编程逻辑器件内，提供单独的输入接口电路，每个外部焊盘（或内部线）提供来自相关输入引脚的集成电路内的信号。输入接口包含驱动上拉和下拉器件的两个多路复用器，每个复用器被耦合以从可编程存储器单元接收输入并具有公共控制线。

18. 发明授权

US5801546A Interconnect architecture for field programmable gate array using variable length conductors 失效
公开(公告)号：US5801546A
公开(公告)日：1998-09-01
申请号：US667571
申请日：1996-06-21
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

19. 发明授权

US5770951A Configuration logic to eliminate signal contention during reconfiguration 失效
标题翻译：在配置过程中消除信号争用的配置逻辑
公开(公告)号：US5770951A
公开(公告)日：1998-06-23
申请号：US847326
申请日：1997-04-23
申请人： Edmond Y. Cheung , Charles R. Erickson
发明人： Edmond Y. Cheung , Charles R. Erickson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177 , G11C8/04
CPC分类号： G06F17/5054 , H03K19/1737 , H03K19/17748 , H03K19/1776 , H03K19/17772
摘要： A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.
摘要翻译：一种在可编程逻辑器件重新配置期间消除信号争用的方法包括以下步骤：将多个存储器单元布置成集合，并且在一个方向上或者在第一方向或第二方向上选择性地编程存储器单元。用于提供选择性编程的结构包括多个同步触发器和多个相关联的双输入多路复用器。提供给多路复用器的第一逻辑状态的控制信号提供通过触发器的第一信号传播方向，而处于第二逻辑状态的控制信号通过触发器提供第二信号传播方向。

20. 发明授权

US5760604A Interconnect architecture for field programmable gate array 失效
标题翻译：现场可编程门阵列的互连架构
公开(公告)号：US5760604A
公开(公告)日：1998-06-02
申请号：US656752
申请日：1996-06-03
申请人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
发明人： Kerry M. Pierce , Charles R. Erickson , Chih-Tsung Huang , Douglas P. Wieland
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.
摘要翻译：提供了FPGA架构，其使用多于一个长度的逻辑单元输出线，并提供扩展线以增加逻辑单元输出线的覆盖范围。该架构允许一个逻辑单元与另一个逻辑单元之间的极快连接。而且，所有逻辑单元输出线驱动大约相同数量的缓冲可编程互连点（PIP），使得可以预测一个逻辑单元与下一个逻辑单元之间的信号延迟，而不管用户选择的功能和路由。 PIP的频率随着与起始逻辑单元的距离增加而减小。这有利于与易于将互联的逻辑紧邻的软件配合。该架构优选地实现为具有在每个瓦片中具有一个逻辑单元的瓦片布局，以及延伸穿过若干瓦片的逻辑单元输入和输出线。因此，一个瓦片边界与另一个瓦片边界相似，并且具有最小层次。

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