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    • 12. 发明申请
    • ILLUMINANT TYPE TRANSPARENT SOLAR CELL DEVICE
    • 发光型透明太阳能电池装置
    • US20110073179A1
    • 2011-03-31
    • US12890148
    • 2010-09-24
    • Hsin-Chun LUChun-Lung ChuChen-Sung ChangJo-Ling LuChen-Yang Lo
    • Hsin-Chun LUChun-Lung ChuChen-Sung ChangJo-Ling LuChen-Yang Lo
    • H01L31/00
    • H01L31/02322H01L31/022466
    • An illuminant transparent solar cell device, comprising a transparent substrate and the following layers disposed from bottom up sequentially on the transparent substrate: a transparent fluorescent layer, a p-type transparent conductive oxide layer, an intrinsic-type transparent conductive oxide layer, a n-type transparent conductive oxide layer, and an anti-reflection layer serving as a protection layer. In the illuminant transparent solar cell device, the characteristics of a p-type and an n-type transparent conductive oxide layers as well as a transparent fluorescent layer are utilized so that sunlight can not only be used to provide natural lighting in daytime but also be used to generate electricity which is stored in an electricity storage device by transmitting through this device while the electricity stored therein can be used to provide indoor lighting at night, thus saving the consumption of fossil fuel energy.
    • 一种透明太阳能电池器件,包括透明基板和从下而上依次设置在透明基板上的透明基板和透明基板上的下列层:透明荧光层,p型透明导电氧化物层,本征型透明导电氧化物层,n 型透明导电氧化物层和用作保护层的防反射层。 在发光体透明太阳能电池器件中,利用p型和n型透明导电氧化物层以及透明荧光层的特性,使得阳光不仅可以用于在白天提供自然光照,而且还可以是 用于通过在该蓄电装置中发送的电力来存储在蓄电装置中的电力,而其中存储的电能可以用于夜间提供室内照明,因此节省了化石燃料的消耗。
    • 15. 发明授权
    • Chemical mechanical polishing process for forming shallow trench isolation structure
    • 用于形成浅沟槽隔离结构的化学机械抛光工艺
    • US07544305B2
    • 2009-06-09
    • US11863665
    • 2007-09-28
    • Chia-Jung HsuArt YuHsiao-Ling LuTeng-Chun Tsai
    • Chia-Jung HsuArt YuHsiao-Ling LuTeng-Chun Tsai
    • B44C1/22
    • H01L21/76229H01L21/31053
    • A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
    • 提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离(STI)多级化学机械抛光(CMP)方法。 所述基板包括致密区域和隔离区域,在所述基板上形成的氮化硅层,形成在所述氮化硅层和所述基板中的多个沟槽,形成在所述基板上方的填充所述沟槽的氧化物层, 密集区域中的沟槽小于隔离区域中的沟槽。 执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。 执行第二抛光步骤以去除氧化硅层的剩余部分的一部分,直到暴露氮化硅层。
    • 20. 发明授权
    • Electrostatic discharge protection circuit
    • 静电放电保护电路
    • US08952457B2
    • 2015-02-10
    • US12181545
    • 2008-07-29
    • Shih-Yu WangChia-Ling LuYan-Yu ChenYu-Lien LiuTao-Cheng Lu
    • Shih-Yu WangChia-Ling LuYan-Yu ChenYu-Lien LiuTao-Cheng Lu
    • H01L23/62H01L27/02
    • H01L27/0266
    • An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.
    • 提供了包括第一导电类型的衬底,第二导电类型的环形阱区域,第一导电类型的两个第一区域和第二导电类型的至少一个晶体管的ESD保护电路。 环形阱区域设置在基板中。 第一区域设置在基板中并被环形区域包围。 至少一个晶体管设置在第一区域之间的衬底上,并且包括源极,栅极和漏极。 环形阱区域和漏极耦合到第一电压源。 源极和第一区域中的一个耦合到第二电压源,并且第一区域中的另一个耦合到衬底触发电路。