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1. 发明授权

US07291870B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US07291870B2
公开(公告)日：2007-11-06
申请号：US10904475
申请日：2004-11-12
申请人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266 , H01L29/7436 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
摘要翻译：耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

2. 发明授权

US07193274B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07193274B2
公开(公告)日：2007-03-20
申请号：US10854792
申请日：2004-05-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

3. 发明申请

US20060273399A1 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
公开(公告)号：US20060273399A1
公开(公告)日：2006-12-07
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

4. 发明授权

US07012305B2 Electro-static discharge protection circuit for dual-polarity input/output pad 有权
标题翻译：用于双极输入/输出板的静电放电保护电路
公开(公告)号：US07012305B2
公开(公告)日：2006-03-14
申请号：US10708171
申请日：2004-02-12
申请人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.
摘要翻译：提供用于双极性I / O焊盘的静电放电（ESD）保护电路。保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

5. 发明申请

US20050269641A1 ELECTROSTATIC PROTECTION CIRCUIT 有权
标题翻译：静电保护电路
公开(公告)号：US20050269641A1
公开(公告)日：2005-12-08
申请号：US10904475
申请日：2004-11-12
申请人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Shin Su , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L27/02 , H01L29/72 , H01L29/74
CPC分类号： H01L27/0266 , H01L29/7436 , H01L29/87
摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.
摘要翻译：耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并且耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

6. 发明申请

US20050133868A1 [ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT FOR DUAL-POLARITY INPUT/OUTPUT PAD] 有权
标题翻译： [双极输入/输出板电静电放电保护电路]
公开(公告)号：US20050133868A1
公开(公告)日：2005-06-23
申请号：US10708171
申请日：2004-02-12
申请人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
发明人： Shin Su , Chun-Hsiang Lai , Chia-Ling Lu , Yen-Hung Yeh , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L23/62 , H01L27/02 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.
摘要翻译：提供用于双极性I / O焊盘的静电放电（ESD）保护电路。保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

7. 发明申请

US20050047036A1 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US20050047036A1
公开(公告)日：2005-03-03
申请号：US10854792
申请日：2004-05-27
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L23/60 , H01L27/02 , H02H9/00
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

8. 发明授权

US07573102B2 ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad 有权
标题翻译： ESD保护结构和方法利用高耐压焊盘的基板触发
公开(公告)号：US07573102B2
公开(公告)日：2009-08-11
申请号：US11496490
申请日：2006-08-01
申请人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
发明人： Meng-Huang Liu , Chun-Hsiang Lai , Shin Su , Yen-Hung Yeh , Chia-Ling Lu , Tao-Cheng Lu
IPC分类号： H01L29/72
CPC分类号： H01L27/0266
摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
摘要翻译：在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

9. 发明授权

US07087968B1 Electrostatic discharge protection circuit and semiconductor circuit therewith 有权
标题翻译：静电放电保护电路及半导体电路
公开(公告)号：US07087968B1
公开(公告)日：2006-08-08
申请号：US11141284
申请日：2005-05-31
申请人： Chun-Hsiang Lai , Yen-Hung Yeh , Chia-Ling Lu
发明人： Chun-Hsiang Lai , Yen-Hung Yeh , Chia-Ling Lu
IPC分类号： H01L23/62
CPC分类号： H01L27/0259 , H01L29/7436
摘要： An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is coupled to a first power source, and the gate of the second silicon controlled rectifier is also coupled to the first power source line.
摘要翻译： ESD保护电路适用于具有第一电源和第二电源的集成电路。 ESD保护电路包括第一可控硅整流器（SCR），第二可控硅整流器和寄生二极管。第一可控硅整流器的栅极耦合到第一电源，并且第二可控硅整流器的栅极也耦合到第一电源线。

10. 发明授权

US07643258B2 Methods and apparatus for electrostatic discharge protection in a semiconductor circuit 有权
标题翻译：半导体电路中的静电放电保护方法和装置
公开(公告)号：US07643258B2
公开(公告)日：2010-01-05
申请号：US11426513
申请日：2006-06-26
申请人： Chun-Hsiang Lai , Chia-Ling Lu
发明人： Chun-Hsiang Lai , Chia-Ling Lu
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), and in some embodiments a second silicon controlled rectifier, and a parasitic diode. The silicon rectifiers as well as the parasitic diode can all be formed using a single well formed in a substrate. Further, the ESD protection circuit can be used in systems that have multiple power sources regardless of the difference in voltage between the power sources.
摘要翻译： ESD保护电路适用于具有第一电源和第二电源的集成电路。 ESD保护电路包括第一可控硅整流器（SCR），并且在一些实施例中包括第二可控硅整流器和寄生二极管。硅整流器以及寄生二极管都可以使用在衬底中形成的单个阱来形成。此外，ESD保护电路可以用于具有多个电源的系统，而不管电源之间的电压差。

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