专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07544305B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07544305B2
公开(公告)日：2009-06-09
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

2. 发明申请

US20080029478A1 CHEMICAL MECHANICAL POLISHING PROCESS FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURE 有权
标题翻译：化学机械抛光工艺形成浅层分离结构
公开(公告)号：US20080029478A1
公开(公告)日：2008-02-07
申请号：US11863665
申请日：2007-09-28
申请人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Jung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： B44C1/22
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

3. 发明授权

US07294575B2 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US07294575B2
公开(公告)日：2007-11-13
申请号：US10752362
申请日：2004-01-05
申请人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： H01L31/461
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

4. 发明申请

US20050148184A1 Chemical mechanical polishing process for forming shallow trench isolation structure 有权
标题翻译：用于形成浅沟槽隔离结构的化学机械抛光工艺
公开(公告)号：US20050148184A1
公开(公告)日：2005-07-07
申请号：US10752362
申请日：2004-01-05
申请人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Chia-Rung Hsu , Art Yu , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/461 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
摘要翻译：提供了一种用于形成浅沟槽隔离结构的浅沟槽隔离（STI）多级化学机械抛光（CMP）方法。所述基板包括致密区域和隔离区域，在所述基板上形成的氮化硅层，形成在所述氮化硅层和所述基板中的多个沟槽，形成在所述基板上方的填充所述沟槽的氧化物层，密集区域中的沟槽小于隔离区域中的沟槽。执行第一抛光步骤以除去氧化硅层的一部分直到氧化物层的剩余部分的厚度达到预定厚度。执行第二抛光步骤以去除氧化硅层的剩余部分的一部分，直到暴露氮化硅层。

5. 发明授权

US06913978B1 Method for forming shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的形成方法
公开(公告)号：US06913978B1
公开(公告)日：2005-07-05
申请号：US10788183
申请日：2004-02-25
申请人： Neng-Kuo Chen , Hsiu-Chuan Chu , Chih-An Huang , Hsiao-Ling Lu , Teng-Chun Tsai
发明人： Neng-Kuo Chen , Hsiu-Chuan Chu , Chih-An Huang , Hsiao-Ling Lu , Teng-Chun Tsai
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/76235 , H01L21/76232
摘要： A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.
摘要翻译：公开了一种制造浅沟槽隔离结构的方法。在衬底上，依次形成衬垫氧化物层和掩模层。衬垫氧化物层，掩模层和衬底的一部分被图案化以形成沟槽。在进行快速湿热处理之后，在衬底的暴露表面上形成衬垫层，包括在沟槽中的衬底的暴露的硅表面以及掩模层的侧壁和表面。在沟槽和衬底上沉积氧化物层并填充沟槽。进行平坦化处理，直到掩模层被曝光。去除掩模层和焊盘氧化物层以完成浅沟槽隔离结构。

6. 发明申请

US20050054277A1 Polishing pad and method of polishing wafer 审中-公开
标题翻译：抛光垫及抛光方法
公开(公告)号：US20050054277A1
公开(公告)日：2005-03-10
申请号：US10655806
申请日：2003-09-04
申请人： Teng-Chun Tsai , Hsiao-Ling Lu , Shin-Ku Chu , Gene Li
发明人： Teng-Chun Tsai , Hsiao-Ling Lu , Shin-Ku Chu , Gene Li
IPC分类号： B24B37/04 , B24D7/06 , B24B5/00
CPC分类号： B24B37/245 , B24B37/042
摘要： A wafer polishing method is provided. A first polishing pad comprising a plurality of abrasive units is provided. A first polishing operation is performed on the first polishing pad to planarize a wafer. Thereafter, a second polishing pad comprising a plurality of abrasive units is provided. The surface of the abrasive unit in contact with the wafer is roughened. A second polishing operation is performed on the second polishing pad. Since a second polishing operation using a second polishing pad with a roughened surface is performed, gradual reduction of polishing rate as the polish layer is planarized can be avoided.
摘要翻译：提供了晶片抛光方法。提供了包括多个研磨单元的第一抛光垫。在第一抛光垫上执行第一抛光操作以使晶片平坦化。此后，提供包括多个研磨单元的第二抛光垫。与晶片接触的研磨单元的表面被粗糙化。在第二抛光垫上执行第二抛光操作。由于进行使用具有粗糙面的第二研磨垫的第二研磨操作，因此可以避免抛光层平坦化时的抛光速度的逐渐降低。

7. 发明授权

US06249138B1 Method for testing leakage current caused self-aligned silicide 有权
标题翻译：泄漏电流测试方法引起自对准硅化物
公开(公告)号：US06249138B1
公开(公告)日：2001-06-19
申请号：US09447846
申请日：1999-11-23
申请人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
发明人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
IPC分类号： G01R3126
CPC分类号： G01R31/2648
摘要： A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.
摘要翻译：描述了由自对准硅化物工艺引起的漏电流的测试方法。本发明使用不同的测试结构来监测由自对准硅化物工艺引起的漏电流的程度和原因。在监视对没有LDD区域的金属氧化物半导体晶体管进行的自对准硅化物处理的同时，除了考虑从金属硅化物层发生到结以及在金属硅化物层的边缘处发生的漏电流之外，本发明进一步考虑在金属硅化物层的角落处的漏电流。对于具有LDD区域的金属氧化物半导体晶体管，本发明还考虑了从金属硅化物层到LDD区域的漏电流。本发明监测金属硅化物层的角落处的漏电流。

8. 发明申请

US20060172526A1 Method for preventing edge peeling defect 审中-公开
标题翻译：防止边缘剥落缺陷的方法
公开(公告)号：US20060172526A1
公开(公告)日：2006-08-03
申请号：US11331361
申请日：2006-01-13
申请人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
发明人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/0209 , H01L21/02087 , H01L21/76883
摘要： A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.
摘要翻译：本发明公开了一种改善边缘剥离缺陷的方法。根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。

9. 发明申请

US20050085163A1 Method for preventing edge peeling defect 审中-公开
标题翻译：防止边缘剥落缺陷的方法
公开(公告)号：US20050085163A1
公开(公告)日：2005-04-21
申请号：US10685588
申请日：2003-10-16
申请人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
发明人： Chia-Lin Hsu , Shu-Hsien Lee , Chien-Chien Tsai , Hsiao-Ling Lu
IPC分类号： B24B49/00 , B24B51/00 , H01L21/02
CPC分类号： H01L21/0209 , H01L21/02087
摘要： A method for improving edge peeling defect is disclosed in this invention. According to this invention, a wafer can be kept from the edge peeling defect of the prior art by introducing a step for removing the weakly adhesive films and the metal structures at the wafer edge after forming a metal interconnect layer on the wafer. Thus, this invention can raise the yield of semiconductor manufacturing, and reduce the pollution chance of the chamber of the semiconductor manufacture.
摘要翻译：本发明公开了一种改善边缘剥离缺陷的方法。根据本发明，通过在晶片上形成金属互连层之后，通过引入在晶片边缘处去除弱粘合膜和金属结构的步骤，可以保持晶片免受现有技术的边缘剥离缺陷的影响。因此，本发明可以提高半导体制造的产量，并且减少半导体制造室的污染机会。

10. 发明授权

US06235606B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06235606B1
公开(公告)日：2001-05-22
申请号：US09225031
申请日：1999-01-04
申请人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76224
摘要： A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.
摘要翻译：一种制造浅沟槽隔离的方法。在衬底上形成衬垫氧化物层和掩模层。将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。在由沟槽暴露的衬底上形成衬里氧化物层。在衬底上形成隔离层以覆盖衬里氧化物层。隔离层与沟槽保形。在衬底上形成氧化物层以填充沟槽。除去氧化物层和隔离层的一部分直到掩模层露出。去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式