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11. 发明授权

US5371044A Method of uniformly encapsulating a semiconductor device in resin 失效
标题翻译：将半导体器件均匀地封装在树脂中的方法
公开(公告)号：US5371044A
公开(公告)日：1994-12-06
申请号：US876349
申请日：1992-04-30
申请人： Isamu Yoshida , Junichi Saeki , Shigeharu Tsunoda , Kunihiko Nishi , Ichiro Anjoh , Kenichi Imura , Toshihiro Yasuhara , Junichi Arita , Kazuhiro Sugino
发明人： Isamu Yoshida , Junichi Saeki , Shigeharu Tsunoda , Kunihiko Nishi , Ichiro Anjoh , Kenichi Imura , Toshihiro Yasuhara , Junichi Arita , Kazuhiro Sugino
IPC分类号： B29C45/02 , B29C45/14 , H01L21/56 , H01L23/495 , H01L21/58 , H01L21/60
CPC分类号： H01L21/565 , B29C45/14655 , H01L23/4951 , H01L23/49541 , B29C45/02 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L2924/01025 , H01L2924/01079
摘要： A molding method in which a control plate having a size which is equal to or larger than the width of the outlet port of a supply passage are disposed in a cavity adjacent to the resin supply passage of a mold and thereby, the resin molding can be effected substantially equally at upper and lower sides of the insert comprising a semiconductor device and a lead.
摘要翻译：一种模制方法，其中具有等于或大于供应通道的出口宽度的尺寸的控制板设置在与模具的树脂供应通道相邻的空腔中，从而树脂模制件可以在包括半导体器件和引线的插入件的上侧和下侧基本相等地实现。

12. 发明授权

US07803660B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07803660B2
公开(公告)日：2010-09-28
申请号：US12330739
申请日：2008-12-09
申请人： Fumio Murakami , Kenichi Imura , Makoto Araki
发明人： Fumio Murakami , Kenichi Imura , Makoto Araki
IPC分类号： H01L21/00
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2223/54486 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.
摘要翻译：在制造半导体器件的方法中，半导体芯片通过薄膜状抗蚀剂面向上安装在其上形成保护绝缘膜的印刷线路板上，并且多个半导体芯片通过转印共同模制模具技术，当进行传递成型时，在印刷线路板的吸附面和下模之间，使得吸附印刷电路板，通孔从相对的端部附近到达下模的外部空间为了防止连接半导体芯片的电极和印刷电路板的导体图案的接合线的大变形，防止短路和开路，模具腔的浇注模塑树脂形成为尽可能多的浇口。

13. 发明申请

US20090093087A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090093087A1
公开(公告)日：2009-04-09
申请号：US12330739
申请日：2008-12-09
申请人： Fumio MURAKAMI , Kenichi Imura , Makoto Araki
发明人： Fumio MURAKAMI , Kenichi Imura , Makoto Araki
IPC分类号： H01L21/02
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2223/54486 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.
摘要翻译：在制造半导体器件的方法中，半导体芯片通过薄膜状抗蚀剂面向上安装在其上形成保护绝缘膜的印刷线路板上，并且多个半导体芯片通过转印共同模制模具技术，当进行传递成型时，在印刷线路板的吸附面和下模之间，使得吸附印刷电路板，通孔从相对的端部附近到达下模的外部空间为了防止连接半导体芯片的电极和印刷电路板的导体图案的接合线的大变形，防止短路和开路，模具腔的浇注模塑树脂形成为尽可能多的浇口。

14. 发明授权

US07295030B2 Thin film transistor tester and corresponding test method 失效
标题翻译：薄膜晶体管测试仪及相应的测试方法
公开(公告)号：US07295030B2
公开(公告)日：2007-11-13
申请号：US11163996
申请日：2005-11-07
申请人： Kenichi Imura , Daiju Nakano , Yoshitami Sakaguchi
发明人： Kenichi Imura , Daiju Nakano , Yoshitami Sakaguchi
IPC分类号： G01R31/26
CPC分类号： G09G3/006
摘要： To test electrical characteristics of a Thin Film Transistor (TFT) with a source or drain terminal left open and exposed, using a non-contact current source and protecting the TFTs from adverse effects, such as contamination, destruction, and the like. A tester 100 is provided to test a TFT array substrate 14, the tester including ion flow supply devices 16 and 18 for supplying an ion flow onto the surface of a substrate 14. Thereon, an array 12 of TFTs is formed, each TFT being connected to an electrode having a source or a drain left open and exposed; a control circuit 24 for supplying an operating voltage to a gate electrode of the TFT to be tested in the array; and a measurement circuit 24 for measuring an operating current via the testing TFT source or drain that remain in a non open state.
摘要翻译：为了测试具有源极或漏极端子的薄膜晶体管（TFT）的电气特性，其开放并暴露，使用非接触电流源并保护TFT免受诸如污染，破坏等的不利影响。提供测试器100以测试TFT阵列基板14，该测试仪包括用于将离子流提供到基板14的表面上的离子流供应装置16和18。其中，形成TFT的阵列12，每个TFT连接到具有源极或漏极的电极的左侧敞开并暴露; 控制电路24，用于向阵列中要测试的TFT的栅电极提供工作电压; 以及测量电路24，用于测量保持在非打开状态的测试TFT源极或漏极的工作电流。

15. 发明授权

US07282943B2 Inspection device for inspecting TFT 失效
标题翻译：用于检查TFT的检查装置
公开(公告)号：US07282943B2
公开(公告)日：2007-10-16
申请号：US10970555
申请日：2004-10-21
申请人： Yoshitami Sakaguchi , Daiju Nakanao , Kenichi Imura , Yoshinori Mekata , Tomoyuki Taguchi
发明人： Yoshitami Sakaguchi , Daiju Nakanao , Kenichi Imura , Yoshinori Mekata , Tomoyuki Taguchi
IPC分类号： G01R31/00 , G01R31/28 , G09G5/00
CPC分类号： G01R31/2621 , G01R31/2831 , H01L27/12
摘要： Provided is an inspection device which inspects a thin film transistor (TFT) for supplying a current to a light emitting element. The inspection device includes: a first current supply circuit which supplies a drain current between a drain and a source of the TFT; a gate voltage adjustment circuit which adjust a gate voltage to be applied to a gate of the TFT so as to allow a predetermined specified current to flow between the drain and source of the TFT; and a measurement unit which measures the gate voltage adjusted by the gate voltage adjustment circuit.
摘要翻译：提供了检查用于向发光元件供给电流的薄膜晶体管（TFT）的检查装置。检查装置包括：第一电流供给电路，其在TFT的漏极和源极之间提供漏极电流; 栅极电压调整电路，其调整施加到TFT的栅极的栅极电压，以允许预定的规定电流在TFT的漏极和源极之间流动; 以及测量单元，其测量由栅极电压调节电路调节的栅极电压。

16. 发明申请

US20060108430A1 Electronic device and method of manufacturing the same 有权
公开(公告)号：US20060108430A1
公开(公告)日：2006-05-25
申请号：US11326448
申请日：2006-01-06
申请人： Takahiro Osawa , Yoichi Kawata , Atsushi Fujishima , Tamaki Wada , Kenichi Imura
发明人： Takahiro Osawa , Yoichi Kawata , Atsushi Fujishima , Tamaki Wada , Kenichi Imura
IPC分类号： G06K19/06
CPC分类号： G06K19/07732 , B29C45/14647 , G06K19/077 , G06K19/07745 , H01L23/04 , H01L23/13 , H01L23/3107 , H01L23/5388 , H01L24/48 , H01L25/0652 , H01L25/50 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2225/06562 , H01L2924/00014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/3511 , Y10T29/4913 , Y10T29/49133 , Y10T29/49146 , Y10T29/49158 , Y10T29/49222 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： A memory card wherein a substrate is affixed to a cap is formed without the projection of substrate edges from a back surface of the cap. The memory card includes a substrate having a sealing member bonded to a recess in the cap. By utilizing a difference in thermal expansion coefficient between the sealing member and the substrate, the substrate is warped so that its central portion projects away from the cap. The shallow recess is deeper than the sum of the thickness of the substrate and the thickness of an adhesive for bonding the substrate to the bottom of the shallow recess, whereby peripheral edges of the substrate retract into the shallow recess without projecting from the back surface of the cap. The cap is shaped as a card several millimeters thick. A memory chip and control chip are incorporated in the sealing member.

17. 发明申请

US20060097745A1 THIN FILM TRANSISTOR TESTER AND CORRESPONDING TEST METHOD 失效
标题翻译：薄膜晶体管测试仪和相应的测试方法
公开(公告)号：US20060097745A1
公开(公告)日：2006-05-11
申请号：US11163996
申请日：2005-11-07
申请人： Kenichi Imura , Daiju Nakano , Yoshitami Sakaguchi
发明人： Kenichi Imura , Daiju Nakano , Yoshitami Sakaguchi
IPC分类号： G01R31/00
CPC分类号： G09G3/006
摘要： To test electrical characteristics of a Thin Film Transistor (TFT) with a source or drain terminal left open and exposed, using a non-contact current source and protecting the TFTs from adverse effects, such as contamination, destruction, and the like. A tester 100 is provided to test a TFT array substrate 14, the tester including ion flow supply devices 16 and 18 for supplying an ion flow onto the surface of a substrate 14. Thereon, an array 12 of TFTs is formed, each TFT being connected to an electrode having a source or a drain left open and exposed; a control circuit 24 for supplying an operating voltage to a gate electrode of the TFT to be tested in the array; and a measurement circuit 24 for measuring an operating current via the testing TFT source or drain that remain in a non open state.
摘要翻译：为了测试具有源极或漏极端子的薄膜晶体管（TFT）的电气特性，其开放并暴露，使用非接触电流源并保护TFT免受诸如污染，破坏等的不利影响。提供测试器100以测试TFT阵列基板14，该测试仪包括用于将离子流提供到基板14的表面上的离子流供应装置16和18。其中，形成TFT的阵列12，每个TFT连接到具有源极或漏极的电极的左侧敞开并暴露; 控制电路24，用于向阵列中要测试的TFT的栅电极提供工作电压; 以及测量电路24，用于测量保持在非打开状态的测试TFT源极或漏极的工作电流。

18. 发明授权

US07015069B2 Method of manufacturing a semiconductor device and a semiconductor device 有权
公开(公告)号：US07015069B2
公开(公告)日：2006-03-21
申请号：US11047660
申请日：2005-02-02
申请人： Noriyuki Takahashi , Masayuki Suzuki , Kouji Tsuchiya , Takao Matsuura , Takanori Hashizume , Masahiro Ichitani , Kazunari Suzuki , Takafumi Nishita , Kenichi Imura , Takashi Miwa
发明人： Noriyuki Takahashi , Masayuki Suzuki , Kouji Tsuchiya , Takao Matsuura , Takanori Hashizume , Masahiro Ichitani , Kazunari Suzuki , Takafumi Nishita , Kenichi Imura , Takashi Miwa
IPC分类号： H01L21/44
CPC分类号： H01L23/564 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2223/5442 , H01L2223/54473 , H01L2224/16 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/92 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/20752 , H01L2924/30105 , H01L2924/351 , H01L2224/83 , H01L2224/85 , H01L2924/00014 , H01L2224/92247 , H01L2924/00 , H01L2924/00012
摘要： The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

19. 发明申请

US20060046340A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060046340A1
公开(公告)日：2006-03-02
申请号：US11213771
申请日：2005-08-30
申请人： Fumio Murakami , Kenichi Imura , Makoto Araki
发明人： Fumio Murakami , Kenichi Imura , Makoto Araki
IPC分类号： H01L21/00
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2223/54486 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In the method of manufacturing a semiconductor device that semiconductor chips are mounted facing-up on the printed wiring board on which a protective insulation film is formed by means of a film-like resist and a plurality of the semiconductor chips are collectively molded by a transfer mold technology, when transfer molding is performed, among the adsorption face of the printed wiring board and the lower die to make adsorb the printed wiring board, the through holes reaching the exterior space of the lower die from the vicinity of the end portion opposing the gate to pour mold resin of a mold cavity are formed as many as possible in order to prevent a short circuit and an open circuit by big deformation of a bonding wire connecting an electrode of the semiconductor chip and an conductor pattern of the printed wiring board.
摘要翻译：在制造半导体器件的方法中，半导体芯片通过薄膜状抗蚀剂面向上安装在其上形成保护绝缘膜的印刷线路板上，并且多个半导体芯片通过转印共同模制模具技术，当进行传递成型时，在印刷线路板的吸附面和下模之间，使得吸附印刷电路板，通孔从相对的端部附近到达下模的外部空间为了防止连接半导体芯片的电极和印刷电路板的导体图案的接合线的大变形，防止短路和开路，模具腔的浇注模塑树脂形成为尽可能多的浇口。

20. 发明授权

US06797542B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06797542B2
公开(公告)日：2004-09-28
申请号：US10364503
申请日：2003-02-12
申请人： Bunshi Kuratomi , Fukumi Shimizu , Kenichi Imura , Katsushige Namiki , Fumio Murakami
发明人： Bunshi Kuratomi , Fukumi Shimizu , Kenichi Imura , Katsushige Namiki , Fumio Murakami
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48471 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要： At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.
摘要翻译：在制造半导体集成电路器件时对矩阵框架进行树脂模制时，将预定量的空气馈送到第一排中的第一空腔和第二排中的第二空腔中的每一个中，第一和第二空腔为在成型模具的下模具中以矩阵形式形成，以便对空腔的内部进行加压，并且将密封树脂装入空腔中，同时其中的压力以这样的方式被调节：密封树脂在所有空腔中变得相等，由此可以稳定所获得的产品的质量。

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