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11. 发明授权

US11237231B2 Z-axis magnetic sensor with distributed flux guides 有权
公开(公告)号：US11237231B2
公开(公告)日：2022-02-01
申请号：US16957719
申请日：2018-12-20
申请人： Robert Bosch GmbH , Anuraag Mohan , Phillip Mather , Guido De Sandre
发明人： Anuraag Mohan , Phillip Mather , Guido De Sandre
IPC分类号： G01R33/09
摘要： An out-of-plane tunneling magnetoresistive (TMR) magnetic field sensor includes a sense element that defines a sense plane and a flux guide configured to direct a magnetic field perpendicular to the sense plane into the sense plane. The magnetic field sensor further includes a first coil arranged in a first plane, a second coil electrically insulated from the first coil and arranged in a spaced-apart second plane, and drive circuitry operatively connected to the first coil and the second coil. The drive circuitry in a first mode energizes the first and second coils to generate respective first and second fields that combine to set a magnetization of the flux guide. The drive circuitry in a second mode energizes only the first coil to generate the first field so as to set a magnetization of the sense element without changing the magnetization of the flux guide.

12. 发明申请

US20120075010A1 DISCHARGE CIRCUIT FOR VOLTAGE MULTIPLIERS 有权
标题翻译：电压放大器放电电路
公开(公告)号：US20120075010A1
公开(公告)日：2012-03-29
申请号：US13222775
申请日：2011-08-31
申请人： Guido DE SANDRE , Luca BETTINI , Gianni GIACOMI
发明人： Guido DE SANDRE , Luca BETTINI , Gianni GIACOMI
IPC分类号： G05F3/02 , H05F3/00
CPC分类号： G11C5/145 , H02M3/073 , H02M2001/322
摘要： An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node. The discharge stage is configured to cause the discharge current flowing through the first discharge circuit branch—during the portion of the discharge phase of the corresponding circuit node—when the pump voltage of the corresponding circuit node is higher than a respective threshold, and through the second discharge circuit branch when the pump voltage of the corresponding circuit node is lower than said respective threshold.
摘要翻译：提出了一种放电电路的实施例，用于在电荷泵关闭期间在放电阶段期间排出累积在电荷泵的电路节点中的电荷。电荷泵配置为在电荷泵的操作阶段期间使每个电路节点偏置相应的泵电压。放电电路包括被配置为在放电阶段期间产生放电电流的发生器电路。放电电路还包括用于在放电阶段的相应部分期间排出存储在电荷泵的每个电路节点中的电荷的装置; 这种用于排气的装置包括用于电荷泵的每个电路节点的相应的放电级。每个放电级包括耦合到相应电路节点的第一放电电路支路和第二放电电路支路。放电级被配置为使得流过第一放电电路的放电电流在相应的电路节点的放电阶段的部分期间 - 当相应的电路节点的泵浦电压高于相应的阈值时分支，并且通过当相应的电路节点的泵浦电压低于所述相应阈值时，第二放电电路分支。

13. 发明授权

US07885116B2 Sense amplifier for low-supply-voltage nonvolatile memory cells 有权
标题翻译：用于低电压 - 非易失性存储器单元的感应放大器
公开(公告)号：US07885116B2
公开(公告)日：2011-02-08
申请号：US12368271
申请日：2009-02-09
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

14. 发明申请

US20080285359A1 Level-shifter circuit and memory device comprising said circuit 有权
标题翻译：电平移位器电路和包括所述电路的存储器件
公开(公告)号：US20080285359A1
公开(公告)日：2008-11-20
申请号：US12152660
申请日：2008-05-14
申请人： Guido De Sandre , Andrea Ambrosino , Marco Pasotti
发明人： Guido De Sandre , Andrea Ambrosino , Marco Pasotti
IPC分类号： G11C7/00 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1057 , G11C7/1084 , H03K3/35613
摘要： A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level.
摘要翻译：电平移动器电路适于将输入电压转换成在负电压值直到预设的正电压电平之间可变的输出电压。移位器电路包括适于将输入电压移动到预设正电压电平的第一电路，适于将预设电压电平传送到连接到预设负电压值的第三电路的第二电路。第三电路以正电平或零电平连接到另一电压，并且适于将输出电压提供到预设的负电平或正电平或零电平。

15. 发明授权

US07088614B2 Programming method for a multilevel memory cell 有权
公开(公告)号：US07088614B2
公开(公告)日：2006-08-08
申请号：US10331161
申请日：2002-12-26
申请人： Guido De Sandre , Marco Poles , David Iezzi , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , David Iezzi , Marco Pasotti
IPC分类号： G11C18/04
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.

16. 发明申请

US20060139982A1 Non-volatile and-type content addressable memory 有权
标题翻译：非易失性和类型内容可寻址存储器
公开(公告)号：US20060139982A1
公开(公告)日：2006-06-29
申请号：US11355419
申请日：2006-02-16
申请人： Guido de Sandre
发明人： Guido de Sandre
IPC分类号： G11C15/00 , G11C15/04 , G11C16/04
CPC分类号： G11C15/046
摘要： In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a ground line, a match control line, and with every row of cells there is associated a search activation terminal and a match indication terminal; a method of controlling the storage and retrieval of data in the memory utilizing a unique comparison strategy for determining when the content of a comparison register is found in the memory.
摘要翻译：为了加快对内容可寻址存储器中的数据项的搜索，并且简化与每行单元相关联的存储器的电路结构，地控制线，地线，匹配控制线以及每行的小区与搜索激活终端和匹配指示终端相关联; 一种利用独特的比较策略来控制存储器中数据的存储和检索的方法，用于确定何时在存储器中找到比较寄存器的内容。

17. 发明授权

US07031177B2 Non-volatile and-type content addressable memory 有权
标题翻译：非易失性和类型内容可寻址存储器
公开(公告)号：US07031177B2
公开(公告)日：2006-04-18
申请号：US10676731
申请日：2003-10-01
申请人： Guido de Sandre
发明人： Guido de Sandre
IPC分类号： G11C15/00
CPC分类号： G11C15/046
摘要： In order to speed up the search for a data item in the memory and simplify the circuit structure of the memory, with each row of cells there is associated a ground control line, a ground line and a match control line. Furthermore, with every row of cells there is associated a search activation terminal and a match indication terminal.
摘要翻译：为了加快对存储器中的数据项的搜索并简化存储器的电路结构，每一行单元都具有地线控制线，地线和匹配控制线。此外，每一行单元都有一个搜索激活终端和一个匹配指示终端。

18. 发明申请

US20060018183A1 Content addressable memory cell 有权
标题翻译：内容可寻址存储单元
公开(公告)号：US20060018183A1
公开(公告)日：2006-01-26
申请号：US10970842
申请日：2004-10-20
申请人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
发明人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
IPC分类号： G11C8/02
CPC分类号： G11C15/04 , G11C13/0004 , G11C14/00 , G11C14/009 , G11C15/046
摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.
摘要翻译：一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

19. 发明授权

US06897710B2 Voltage supply distribution architecture for a plurality of memory modules 失效
标题翻译：用于多个存储器模块的电压分配架构
公开(公告)号：US06897710B2
公开(公告)日：2005-05-24
申请号：US10748697
申请日：2003-12-30
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Gilberto Muzzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Gilberto Muzzi , Marco Poles
IPC分类号： G06F1/26 , G11C5/14 , G11C16/30 , G05F1/10
CPC分类号： G11C16/30 , G06F1/26 , G11C5/145
摘要： An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.
摘要翻译：用于向通过多个电荷泵电路提供的多个存储器模块分配电源电压的架构可以包括双向连接到多个存储器模块的分类块，从该存储器模块可以接收多个电力请求。排序块可以基于优先级来提供排序信号，以驱动多个电荷泵电路并将电源电压分配给多个存储器模块。该架构可以有利地是软件可配置的。

20. 发明授权

US06667903B2 Programming method for a multilevel memory cell 有权
公开(公告)号：US06667903B2
公开(公告)日：2003-12-23
申请号：US10017502
申请日：2001-12-14
申请人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
发明人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C17/146
摘要： It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

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