专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07508716B2 Sense amplifier for low-supply-voltage nonvolatile memory cells 有权
标题翻译：用于低电压 - 非易失性存储器单元的感应放大器
公开(公告)号：US07508716B2
公开(公告)日：2009-03-24
申请号：US10777457
申请日：2004-02-12
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载均具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

2. 发明授权

US06655758B2 Method for storing data in a nonvolatile memory 有权
公开(公告)号：US06655758B2
公开(公告)日：2003-12-02
申请号：US10035909
申请日：2001-12-19
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , PierLuigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , PierLuigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/34 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

3. 发明授权

US07843255B2 Charge pump regulator and circuit structure 有权
标题翻译：电荷泵调节器和电路结构
公开(公告)号：US07843255B2
公开(公告)日：2010-11-30
申请号：US11966117
申请日：2007-12-28
申请人： Marco Poles , Marco Pasotti
发明人： Marco Poles , Marco Pasotti
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/14
摘要： There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.
摘要翻译：公开了一种具有输入信号并且以大于输入信号的值产生输出信号的电荷泵的调节器。电荷泵至少包括一个电容器和至少一个用于充电和放电电容器的装置; 调节器包括在输入处具有离开电荷泵的信号和参考信号的装置。所述装置能够响应于电荷泵的输出信号与所述参考信号之间的差值而产生用于所述至少一个装置的电源信号。

4. 发明授权

US07504862B2 Level shifter translator 有权
标题翻译：电平移位器翻译器
公开(公告)号：US07504862B2
公开(公告)日：2009-03-17
申请号：US11321732
申请日：2005-12-28
申请人： Guido De Sandre , Marco Poles , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , Marco Pasotti
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707 , H03K19/01721
摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.
摘要翻译：该类型的电平移位器转换器包括至少一个第一晶体管和一个第二MOS晶体管，属于与第一公共导通端子连接并连接到第一电位基准的相应电路分支，并且在相应的导通端子上接收输入差分电压，第一晶体管和第二晶体管具有指向具有电流镜的偏置电路的各个电路分支，第三晶体管允许将第二晶体管耦合到所述偏置电路，反相器连接到所述电路的输出端，输出驱动第三晶体管。

5. 发明授权

US06687167B2 EEPROM flash memory erasable line by line 有权
标题翻译： EEPROM闪存可逐行删除
公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/16
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译：一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和下分支。以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为下拉和下部分支作为上拉。

6. 发明授权

US06687159B2 Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor 有权
标题翻译：并联连接的多个存储单元的编程方法及其编程电路
公开(公告)号：US06687159B2
公开(公告)日：2004-02-03
申请号：US10036337
申请日：2001-12-19
申请人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
发明人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/3481 , G11C8/08 , G11C16/12
摘要： A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.
摘要翻译：一种编程多个存储单元的方法并联连接在第一和第二供电基准之间，并且其栅极端子连接在一起，并且通过行解码装置也连接到适于产生字的运算放大器的输出端电压信号，第一参考电压由电荷泵电路提供。编程方法使用包括要编程的单元和运算放大器的程序循环，电荷泵电路因此输出其斜率是单元需求函数的电压斜坡。还提供了一种适于实现该方法的编程电路。

7. 发明申请

US20090154249A1 SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS 有权
标题翻译：用于低电压非易失性存储器单元的感测放大器
公开(公告)号：US20090154249A1
公开(公告)日：2009-06-18
申请号：US12368271
申请日：2009-02-09
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

8. 发明授权

US06535428B2 Sensing circuit for memory cells 有权
标题翻译：存储单元的感应电路
公开(公告)号：US06535428B2
公开(公告)日：2003-03-18
申请号：US09882535
申请日：2001-06-14
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C11/5642
摘要： A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
摘要翻译：一种用于感测存储单元的感测电路，所述感测电路具有可电连接到所述存储单元以接收存储单元电流的第一电路分支，所述第一电路支路具有至少一个第一晶体管，当所述第一电路支路连接到存储器单元基本上以共源共栅配置耦合到存储器单元。偏置电流发生器与第一晶体管可操作地相关联，以迫使偏置电流流过其中。

9. 发明申请

US20060226873A1 Level shifter translator 有权
公开(公告)号：US20060226873A1
公开(公告)日：2006-10-12
申请号：US11321732
申请日：2005-12-28
申请人： Guido De Sandre , Marco Poles , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , Marco Pasotti
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707 , H03K19/01721
摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

10. 发明授权

US07885116B2 Sense amplifier for low-supply-voltage nonvolatile memory cells 有权
标题翻译：用于低电压 - 非易失性存储器单元的感应放大器
公开(公告)号：US07885116B2
公开(公告)日：2011-02-08
申请号：US12368271
申请日：2009-02-09
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式