专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06687167B2 EEPROM flash memory erasable line by line 有权
标题翻译： EEPROM闪存可逐行删除
公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/16
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译：一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和下分支。以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为下拉和下部分支作为上拉。

2. 发明授权

US06687159B2 Method of programming a plurality of memory cells connected in parallel, and a programming circuit therefor 有权
标题翻译：并联连接的多个存储单元的编程方法及其编程电路
公开(公告)号：US06687159B2
公开(公告)日：2004-02-03
申请号：US10036337
申请日：2001-12-19
申请人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
发明人： Marco Pasotti , Giovanni Guaitini , Guido De Sandre , David Iezzi , Marco Poles , Pierluigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/3481 , G11C8/08 , G11C16/12
摘要： A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.
摘要翻译：一种编程多个存储单元的方法并联连接在第一和第二供电基准之间，并且其栅极端子连接在一起，并且通过行解码装置也连接到适于产生字的运算放大器的输出端电压信号，第一参考电压由电荷泵电路提供。编程方法使用包括要编程的单元和运算放大器的程序循环，电荷泵电路因此输出其斜率是单元需求函数的电压斜坡。还提供了一种适于实现该方法的编程电路。

3. 发明授权

US07508716B2 Sense amplifier for low-supply-voltage nonvolatile memory cells 有权
标题翻译：用于低电压 - 非易失性存储器单元的感应放大器
公开(公告)号：US07508716B2
公开(公告)日：2009-03-24
申请号：US10777457
申请日：2004-02-12
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载均具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

4. 发明授权

US06655758B2 Method for storing data in a nonvolatile memory 有权
公开(公告)号：US06655758B2
公开(公告)日：2003-12-02
申请号：US10035909
申请日：2001-12-19
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , PierLuigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , PierLuigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/34 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

5. 发明申请

US20090154249A1 SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS 有权
标题翻译：用于低电压非易失性存储器单元的感测放大器
公开(公告)号：US20090154249A1
公开(公告)日：2009-06-18
申请号：US12368271
申请日：2009-02-09
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

6. 发明授权

US06535428B2 Sensing circuit for memory cells 有权
标题翻译：存储单元的感应电路
公开(公告)号：US06535428B2
公开(公告)日：2003-03-18
申请号：US09882535
申请日：2001-06-14
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C11/5642
摘要： A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
摘要翻译：一种用于感测存储单元的感测电路，所述感测电路具有可电连接到所述存储单元以接收存储单元电流的第一电路分支，所述第一电路支路具有至少一个第一晶体管，当所述第一电路支路连接到存储器单元基本上以共源共栅配置耦合到存储器单元。偏置电流发生器与第一晶体管可操作地相关联，以迫使偏置电流流过其中。

7. 发明授权

US07885116B2 Sense amplifier for low-supply-voltage nonvolatile memory cells 有权
标题翻译：用于低电压 - 非易失性存储器单元的感应放大器
公开(公告)号：US07885116B2
公开(公告)日：2011-02-08
申请号：US12368271
申请日：2009-02-09
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/14
摘要： A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.
摘要翻译：用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载都具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

8. 发明授权

US07088614B2 Programming method for a multilevel memory cell 有权
公开(公告)号：US07088614B2
公开(公告)日：2006-08-08
申请号：US10331161
申请日：2002-12-26
申请人： Guido De Sandre , Marco Poles , David Iezzi , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , David Iezzi , Marco Pasotti
IPC分类号： G11C18/04
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： A programming method of a multilevel memory cell is able to store a plurality of bits in a plurality of levels. The method includes writing a logic value in the multilevel memory cell by setting one of the programming levels thereof, these levels being included in the plurality of levels, with respect to a reference level according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value for the levels is reached. A multilevel memory device includes a plurality of multilevel memory cells organized into sectors, split into a plurality of data units whereon a programming operation is performed in parallel.

9. 发明授权

US06897710B2 Voltage supply distribution architecture for a plurality of memory modules 失效
标题翻译：用于多个存储器模块的电压分配架构
公开(公告)号：US06897710B2
公开(公告)日：2005-05-24
申请号：US10748697
申请日：2003-12-30
申请人： Marco Pasotti , Guido De Sandre , David Iezzi , Gilberto Muzzi , Marco Poles
发明人： Marco Pasotti , Guido De Sandre , David Iezzi , Gilberto Muzzi , Marco Poles
IPC分类号： G06F1/26 , G11C5/14 , G11C16/30 , G05F1/10
CPC分类号： G11C16/30 , G06F1/26 , G11C5/145
摘要： An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.
摘要翻译：用于向通过多个电荷泵电路提供的多个存储器模块分配电源电压的架构可以包括双向连接到多个存储器模块的分类块，从该存储器模块可以接收多个电力请求。排序块可以基于优先级来提供排序信号，以驱动多个电荷泵电路并将电源电压分配给多个存储器模块。该架构可以有利地是软件可配置的。

10. 发明授权

US06667903B2 Programming method for a multilevel memory cell 有权
公开(公告)号：US06667903B2
公开(公告)日：2003-12-23
申请号：US10017502
申请日：2001-12-14
申请人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
发明人： Guido De Sandre , Marco Pasotti , Pier Luigi Rolandi , Giovani Guaitini , David Iezzi , Marco Poles
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5635 , G11C17/146
摘要： It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m−1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m−1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式