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    • 1. 发明授权
    • EEPROM flash memory erasable line by line
    • EEPROM闪存可逐行删除
    • US06687167B2
    • 2004-02-03
    • US10225513
    • 2002-08-20
    • Giovanni GuaitiniMarco PasottiGuido De SandreDavid IezziMarco PolesPier Luigi Rolandi
    • Giovanni GuaitiniMarco PasottiGuido De SandreDavid IezziMarco PolesPier Luigi Rolandi
    • G11C1604
    • G11C16/08G11C16/16
    • A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
    • 一种非易失性半导体存储器件,包括连接到行线和两个电源端子的输出。 每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。 为了允许逐行擦除存储器,而不必使用能够承受高电压的部件,每个基本级具有两个辅助MOS晶体管,即上部支路中的n沟道晶体管和 下分支。 以这种方式,可以以这种方式偏置基本级,在读取和编程阶段,上部分支将用作上拉和下部分支作为下拉,而在擦除阶段,上部分支作为 下拉和下部分支作为上拉。