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121. 发明授权

US07036218B2 Method for producing a wafer interposer for use in a wafer interposer assembly 失效
标题翻译：用于制造用于晶片插入器组件的晶片插入器的方法
公开(公告)号：US07036218B2
公开(公告)日：2006-05-02
申请号：US10373414
申请日：2003-02-24
申请人： John L. Pierce
发明人： John L. Pierce
IPC分类号： H01R9/00 , H05K3/00
CPC分类号： G01R1/0433 , G01R1/0483 , H01L2224/45124 , H01L2224/48137 , H01L2224/48235 , H01L2924/01079 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , Y10T29/49004 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49151 , Y10T29/49156 , Y10T29/49162 , H01L2924/00
摘要： A method for producing a wafer interposer (210) for use in a wafer interposer assembly is disclosed. The wafer interposer (210) is produced by attaching solder bumps (140) to a lower surface of a support (120). First electrical terminals (130) are attached to an upper surface of the support (120) and substantially correspond to the solder bumps (140). First electrical pathways are provided that passes through the support (120) and connect the solder bumps (140) to the first electrical terminals (130). Second electrical terminals (310) are attached to the upper surface of the support (120). Second electrical pathways (320) connect the first electrical terminals (130) to the second electrical terminals (310).
摘要翻译：公开了一种用于制造用于晶片内插器组件的晶片插入器（210）的方法。通过将焊料凸块（140）附接到支撑件（120）的下表面来制造晶片插入器（210）。第一电端子（130）附接到支撑件（120）的上表面并且基本上对应于焊料凸块（140）。提供通过支撑件（120）并将焊料凸块（140）连接到第一电端子（130）的第一电路。第二电端子（310）附接到支撑件（120）的上表面。第二电路（320）将第一电端子（130）连接到第二电端子（310）。

122. 发明授权

US07034520B1 Integrated circuit tester 有权
标题翻译：集成电路测试仪
公开(公告)号：US07034520B1
公开(公告)日：2006-04-25
申请号：US11223421
申请日：2005-09-09
申请人： Wayne H. Miller , Chris S. Paretich , James K. Lubin , Stuart M. Firestone
发明人： Wayne H. Miller , Chris S. Paretich , James K. Lubin , Stuart M. Firestone
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/0433
摘要： A product change tool for selectively engaging a product change element with an IC tester interface and disengaging the product change element from the tester interface includes a mobile frame mounted to a base frame and constrained to move relative to the base frame along an axis of linear movement, and a force mechanism for urging the mobile frame to move along the axis of linear movement relative to the base frame. The force mechanism includes first and second links pivotally connected together at their proximal ends and secured at their distal ends to the mobile frame and the base frame respectively. The distal ends of the links are spaced apart along the axis of linear movement and the proximal ends of the links are between the distal ends relative to that axis. An actuator is coupled to the proximal ends of the links for urging the proximal ends of the links in directions transverse to the axis of linear movement, whereby the spacing of the distal ends of the links along the axis changes and the mobile frame moves relative to the base frame along the axis.
摘要翻译：用于选择性地将产品更换元件与IC测试器接口接合并将产品更换元件与测试器接口分离的产品更换工具包括安装到基座框架并被限制为沿着线性运动的轴线相对于基座移动的移动框架以及用于推动移动框架相对于基架沿着线性运动的轴线移动的力机构。力机构包括在其近端处枢转地连接在一起并且在其远端处分别固定到移动框架和基架的第一和第二连杆。连杆的远端沿着线性运动的轴线间隔开，并且连杆的近端相对于该轴线位于远端之间。致动器联接到链节的近端，用于在横向于线性运动的轴线的方向上推动链节的近端，由此沿着轴线的链节的远端的间隔改变，并且移动框架相对于沿着轴的基架。

123. 发明授权

US06983536B2 Method and apparatus for manufacturing known good semiconductor die 失效
标题翻译：用于制造已知的良好半导体管芯的方法和装置
公开(公告)号：US06983536B2
公开(公告)日：2006-01-10
申请号：US10847969
申请日：2004-05-18
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H05K3/30
CPC分类号： H01L23/49838 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/06711 , G01R1/0735 , G01R3/00 , G01R31/2863 , G01R31/287 , G01R31/2889 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , Y10T29/49117 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , H01L2924/00 , H01L2224/05599
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

124. 发明申请

US20050248005A1 Integrated circuit leadframes patterned for measuring the accurate amplitude of changing currents 审中-公开
公开(公告)号：US20050248005A1
公开(公告)日：2005-11-10
申请号：US11154189
申请日：2005-06-16
申请人： Kambiz Hayat-Dawoodi
发明人： Kambiz Hayat-Dawoodi
IPC分类号： G01R1/04 , G01R15/20 , H01L23/495
CPC分类号： G01R15/202 , G01R1/0433 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit penetrating the whole thickness of the pad and substantially traversing the area of the pad from one edge to the opposite edge. This slit is wide enough to interrupt electron flow in the pad plane, but not wide enough to significantly reduce thermal conduction in a direction normal to the pad plane, whereby the slit is operable to disrupt eddy currents induced in the pad by the changing magnetic field. A semiconductor device intended for operation in a changing magnetic field, comprising a leadframe with a chip mount pad having at least one slit in a configuration operable to suppress eddy currents induced in the pad by the changing magnetic field; an integrated circuit chip, having an active and a passive surface; the passive surface attached to the mount pad by a polymeric material; and the active surface having a Hall structure including current and voltage terminals integrated into the circuit, whereby the changing magnetic field can be measured without diminution by said eddy currents.

125. 发明申请

US20050202716A1 Insert and electronic component handling apparatus provided with the same 失效
标题翻译：插入式及电子部件处理装置
公开(公告)号：US20050202716A1
公开(公告)日：2005-09-15
申请号：US10929724
申请日：2004-08-31
申请人： Noboru Saito
发明人： Noboru Saito
IPC分类号： G01R31/26 , G01R1/04 , H01L21/67 , H01L21/68 , H01R13/62
CPC分类号： G01R1/0433 , G01R31/2893 , H05K7/02
摘要： To provide a guide core capable of being detachably attached to an insert body and an insert body to which the guide core can be detachably attached, the present invention provides a guide core able to be attached in a detachable way to an insert body, comprising a supporting portion capable of supporting an external terminal face of an area array type electronic component so that external terminals of the area array type electronic component are exposed to the direction of connection terminals of a socket, and a hook receiver able to be engaged in a releasable way with a hook portion provided to the insert body, and an insert body able to be attached in a detachable way with the guide core, comprising an electronic component guide portion comprising a guide core attachment socket to which the guide core is attached, and an electronic component inlet connected with the guide core attachment socket so that an electronic component can be guided to the guide core attached to the guide core attachment socket, and a hook portion able to be engaged in a releasable way with a hook receiver provided to the guide core.
摘要翻译：为了提供能够可拆卸地附接到插入体和导向芯可拆卸地附接到的插入体的引导芯，本发明提供一种能够以可拆卸的方式附接到插入体上的引导芯，包括支撑部分，其能够支撑区域阵列型电子部件的外部端子面，使得区域阵列型电子部件的外部端子暴露于插座的连接端子的方向;以及钩接收器，其能够接合在可释放的具有设置在插入体上的钩部，以及能够以可拆卸的方式与引导芯连接的插入体，包括电子部件引导部，该电子部件引导部包括引导芯附接到的引导芯附接插座，电子部件入口与引导芯附接插座连接，使得电子部件可以被引导到附接到引导件cor的引导芯 e连接插座，以及能够以可释放的方式与设置在引导芯上的钩接收器接合的钩部。

126. 发明申请

US20050167816A1 Method for making a socket to perform testing on integrated circuits 失效
公开(公告)号：US20050167816A1
公开(公告)日：2005-08-04
申请号：US11090614
申请日：2005-03-25
申请人： Igor Khandros , Gaetan Mathieu , Carl Reynolds
发明人： Igor Khandros , Gaetan Mathieu , Carl Reynolds
IPC分类号： G01R1/04 , G01R1/073 , G01R3/00 , H01L21/44 , H01L29/40
CPC分类号： G01R3/00 , G01R1/0433 , G01R1/0483 , G01R1/07378 , G01R31/2863 , H01L24/13 , H01L2224/131 , H01L2924/01046 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169 , Y10T29/49179 , Y10T29/49197 , Y10T29/49204 , Y10T29/4921 , Y10T29/49211 , Y10T29/49224 , Y10T29/53217 , Y10T29/53265 , H01L2924/014
摘要： A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

127. 发明授权

US06920689B2 Method for making a socket to perform testing on integrated circuits 失效
标题翻译：一种套接字在集成电路上进行测试的方法
公开(公告)号：US06920689B2
公开(公告)日：2005-07-26
申请号：US10310791
申请日：2002-12-06
申请人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
发明人： Igor Y. Khandros , Gaetan L. Mathieu , Carl V. Reynolds
IPC分类号： G01R1/04 , G01R1/073 , G01R3/00 , H01R43/02
CPC分类号： G01R3/00 , G01R1/0433 , G01R1/0483 , G01R1/07378 , G01R31/2863 , H01L24/13 , H01L2224/131 , H01L2924/01046 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169 , Y10T29/49179 , Y10T29/49197 , Y10T29/49204 , Y10T29/4921 , Y10T29/49211 , Y10T29/49224 , Y10T29/53217 , Y10T29/53265 , H01L2924/014
摘要： A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.
摘要翻译：互连结构廉价地制造并且容易地插入到插座中。通过形成具有由具有与空腔对应的开口的掩模材料覆盖的空腔的牺牲衬底来制造互连结构。通过沉积导电材料，然后在开口内连接线并通过沉积更多导电材料进行另一电镀工艺来执行第一电镀工艺。通过首先去除掩模材料和牺牲衬底来完成互连结构。电线的端部与现在形成的接触结构相对联接到电路板。要完成插座，支持设备耦合到电路板以保持测试的集成电路。

128. 发明申请

US20050129301A1 Electronic part inspection device 失效
标题翻译：电子部件检查装置
公开(公告)号：US20050129301A1
公开(公告)日：2005-06-16
申请号：US10506809
申请日：2003-03-07
申请人： Yukio Kanno , Yoshiaki Fukukawa
发明人： Yukio Kanno , Yoshiaki Fukukawa
IPC分类号： G01M99/00 , G01R1/04 , G01R31/01 , G01R31/28 , B65G43/08 , G01M19/00 , G01N21/84 , H01L21/66
CPC分类号： G01R31/2893 , G01R1/0433 , G01R31/01 , G01R31/2851
摘要： An electronic component inspection apparatus includes an inspection socket which inspects a component, a tray disposition area in which a component waits before it is inspected, tray disposition areas which store a component after it has been inspected, components transfer mechanisms each of which has a vacuum or suction nozzle that can pick up and hold a component to transfer the component, a component position confirmation camera which can capture an image of the component that is being transferred, and a controller which transfers a component to the inspection socket, via a position in which the component position confirmation camera captures an image of the component being held by the suction nozzle while the component is being transferred from the tray disposition area to the inspection socket, and based on that captured image, controls the drive of the components transfer mechanisms so that the component is set in the inspection socket.
摘要翻译：电子部件检查装置包括检查部件的检查插座，检查前部件等待的托盘配置区域，检查部件之后存储部件的托盘配置区域，每个具有真空的部件传送机构或可吸收和保持组件以传送组件的吸嘴，可捕获正在传送的组件的图像的组件位置确认摄像机以及通过位置中的位置将组件传送到检查插座的控制器组件位置确认摄像机捕获由吸嘴保持的部件的图像，同时将部件从托盘配置区域传送到检查插座，并且基于该捕获的图像，控制部件传送机构的驱动组件被设置在检查插座中。

129. 发明申请

US20050116328A1 Substrate and method of manufacture thereof 审中-公开
标题翻译：基材及其制造方法
公开(公告)号：US20050116328A1
公开(公告)日：2005-06-02
申请号：US11000038
申请日：2004-12-01
申请人： Kenichi Oi , Hirotaka Jiten
发明人： Kenichi Oi , Hirotaka Jiten
IPC分类号： H01L21/66 , G01R1/04 , H01L23/14 , H05K1/05 , H05K3/28 , H05K3/44 , G01R31/26 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/02
CPC分类号： H05K1/053 , G01R1/0433 , H01L23/142 , H01L2224/48091 , H01L2224/48472 , H01L2924/09701 , H01L2924/00014 , H01L2924/00
摘要： A substrate of the present invention includes an electrically-insulating glass layer formed on both sides of a stainless-plate measuring substrate. The substrate also has a wiring pattern on the electrically-insulating glass layer, and an overcoat glass layer covering the wiring pattern. Thus, the present invention provides a substrate that is inexpensive, can withstand a high temperature of about 400° C. in EM evaluations and the like, and can easily be provided in a large size.
摘要翻译：本发明的基板包括形成在不锈钢板测量基板两侧的电绝缘玻璃层。基板还具有在电绝缘玻璃层上的布线图案和覆盖布线图案的外涂层玻璃层。因此，本发明提供廉价的基板，能够在EM评价等中耐受约400℃的高温，并且可以容易地提供大尺寸。

130. 发明授权

US06824395B2 Semiconductor device-socket 失效
标题翻译：半导体器件插座
公开(公告)号：US06824395B2
公开(公告)日：2004-11-30
申请号：US10167433
申请日：2002-06-13
申请人： Kazumi Uratsuji
发明人： Kazumi Uratsuji
IPC分类号： H01R1200
CPC分类号： H05K7/1023 , G01R1/0433
摘要： A semiconductor device-socket is provided, in which a partition wall for dividing slits engaged with a contact portion of a contact terminal in an object under test-accommodation member has a slope for guiding leads of a semiconductor device onto the contact portion of an adjacent contact terminal.
摘要翻译：提供了一种半导体器件插座，其中用于分隔狭缝的分隔壁与接合端子的接触端子的接触部分接合在被测物体下方具有用于将半导体器件的引线引导到相邻的接触部分的接触部分上的斜面接触端子

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