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111. 发明申请

US20060204650A1 Electrical connector structure of circuit board and method for fabricating the same 有权
公开(公告)号：US20060204650A1
公开(公告)日：2006-09-14
申请号：US11370532
申请日：2006-03-08
申请人： Wen-Hung Hu
发明人： Wen-Hung Hu
IPC分类号： B05D5/12 , C23C26/00 , C25D5/02
CPC分类号： H05K3/243 , C23C26/00 , C23C28/00 , C23C28/021 , C23C28/023 , C25D5/02 , C25D7/12 , H01L2924/0002 , H05K1/111 , H05K3/108 , H05K3/28 , H05K3/388 , H05K3/4007 , H05K2203/0571 , H05K2203/0574 , H05K2203/0577 , H05K2203/0597 , Y10T428/24917 , H01L2924/00
摘要： An electrical connector structure of circuit board and a method for fabricating the same are proposed. A circuit board having a conductive layer is formed with a first resist layer and a second resist layer thereon, so as to form electrical connection pads and metal bumps on the electrical connection pads. The first and second resist layers are formed with openings therein at positions corresponding to the electrical connection pads and metal bumps, and the exposed conductive layer is removed. An adhesive layer is formed to cover the exposed surfaces of the electrical connection pads and the metal bumps. Then, the second resist layer, the first resist layer and the conductive layer covered by the first resist layer are removed. Later, an insulating protective layer is formed on a surface of the circuit board, and thinned to expose a portion of the adhesive layer, such that electrical connectors of the circuit board are fabricated.

112. 发明授权

US07091583B2 Method and structure for prevention leakage of substrate strip 有权
标题翻译：衬底条防止泄漏的方法和结构
公开(公告)号：US07091583B2
公开(公告)日：2006-08-15
申请号：US10933349
申请日：2004-09-03
申请人： Ying-Chih Chen , Yun-Hsiang Tien , Ming-Jiun Lai , Yi-Chuan Ding
发明人： Ying-Chih Chen , Yun-Hsiang Tien , Ming-Jiun Lai , Yi-Chuan Ding
IPC分类号： H01L23/02
CPC分类号： H01L24/97 , H01L23/49838 , H01L23/5386 , H01L23/544 , H01L23/60 , H01L2223/54473 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H05K1/0269 , H05K3/0047 , H05K3/0052 , H05K3/06 , H05K3/242 , H05K3/28 , H05K2201/09918 , H05K2203/0574 , H05K2203/175 , H01L2924/00
摘要： The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer. By removing the exposed portion of the plating bus, the breaking hole is formed to electrically isolate the extended trail from the contact pads in order to prevent a chip on the substrate strip from being damaged by ESD (Electrostatic Discharge) during packaging processes.
摘要翻译：本发明提供了一种用于防止衬底条的泄漏的结构和方法。衬底条包括边缘部分和多个单元。衬底条表面上的图案化金属层包括延伸到边缘部分的至少一个电镀母线，在该单元处的多条电镀线，在该单元处的多个接触焊盘和在边缘部分处的多个基准标记。电镀母线具有一个伸出的线，其一端暴露在衬底带的侧壁外。基准标记和接触垫从焊料掩模的多个第一开口露出。焊接掩模还在边缘部分处具有暴露电镀总线的一部分以限定断裂孔的第二开口。在基准标记和接触焊盘上形成表面层之后，电镀总线的露出部分没有表面层。通过去除电镀总线的暴露部分，形成断开孔以将延伸的迹线与接触焊盘电隔离，以防止在封装过程中ESD（静电放电）在衬底条上的芯片被损坏。

113. 发明申请

US20060030069A1 Packaging method for manufacturing substrates 审中-公开
标题翻译：制造基板的包装方法
公开(公告)号：US20060030069A1
公开(公告)日：2006-02-09
申请号：US10912602
申请日：2004-08-04
申请人： Chien-Wei Chang
发明人： Chien-Wei Chang
IPC分类号： H01L21/50
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2924/0002 , H05K1/113 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4602 , H05K2201/0352 , H05K2201/09509 , H05K2201/09563 , H05K2201/09736 , H05K2203/0574 , H05K2203/1581 , H01L2924/00
摘要： A method for manufacturing IC substrate is provided, including using the bottom plating technique to form copper columns to elevate the bump pads in the micro opening to the surface level of the solder resist. The metal column can act as a stress buffer induced by the temperature profile during the IC packaging process. The metal column can also solve the problems of insufficient bonding strength to the bump pad and the inapplicable solder due to the printing technique restriction. The metal column elevates the bump pad to the surface level of the solder resist so that the under fill after bonding the chip can be performed more easily. The present invention can improve the yield rate and the density of the packaging and is suitable for the next generation, including nano-scale electronic products.
摘要翻译：提供了一种用于制造IC基板的方法，包括使用底镀技术形成铜柱，以将微孔中的凸块焊盘升高到阻焊剂的表面水平。在IC封装过程中，金属柱可以作为由温度分布引起的应力缓冲液。金属柱也可以解决由于印刷技术的限制而对凸块焊盘和不适用的焊料的接合强度不足的问题。金属柱将凸块焊盘提升到阻焊剂的表面水平，使得可以更容易地进行粘合芯片后的下填充。本发明可以提高包装的产率和密度，适用于下一代，包括纳米级电子产品。

114. 发明申请

US20060017151A1 BGA package board and method for manufacturing the same 有权
标题翻译： BGA封装板及其制造方法
公开(公告)号：US20060017151A1
公开(公告)日：2006-01-26
申请号：US10969403
申请日：2004-10-20
申请人： Kyoung-Ro Yoon , Young-Hwan Shin , Tae-Gon Lee
发明人： Kyoung-Ro Yoon , Young-Hwan Shin , Tae-Gon Lee
IPC分类号： H01L23/12 , H01L21/50
CPC分类号： H05K3/243 , H01L21/4853 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/05155 , H01L2224/05599 , H01L2224/05644 , H01L2224/05647 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/484 , H01L2224/73265 , H01L2224/85444 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H05K3/061 , H05K3/28 , H05K3/427 , H05K3/429 , H05K3/4652 , H05K2201/0352 , H05K2201/09536 , H05K2201/09736 , H05K2203/0353 , H05K2203/0574 , H05K2203/0577 , Y10T29/49128 , Y10T29/4913 , Y10T29/49135 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.
摘要翻译：本文公开了一种球栅阵列（BGA）封装板。 BGA封装板包括：第一外层，其上形成包括电路图案和引线焊盘图案的图案;第二外层，其上形成包括电路图案和焊球图案的图案;绝缘层形成在第一和第二外部层之间的第一外部通孔，用于将第一和第二外部层彼此电连接的第一外部通孔，以及形成在第一和第二外部层中的每一个上的阻焊层，其中阻焊层的一部分对应于引线焊盘图案和焊球图案打开。焊球焊盘图案比第二外层的电路图形薄。

115. 发明申请

US20050167803A1 Film substrate, fabrication method thereof, and image display substrate 失效
标题翻译：薄膜基板，其制造方法和图像显示基板
公开(公告)号：US20050167803A1
公开(公告)日：2005-08-04
申请号：US11043946
申请日：2005-01-28
申请人： Hiroyuki Imamura
发明人： Hiroyuki Imamura
IPC分类号： H01L21/60 , G02F1/13 , G02F1/1345 , H01L23/34 , H01L23/498 , H05K1/00 , H05K1/02 , H05K1/11 , H05K3/00 , H05K3/10 , H05K3/24 , H05K3/36
CPC分类号： H05K1/189 , G02F1/13452 , H01L23/4985 , H01L24/29 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/83101 , H01L2224/838 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0781 , H01L2924/19043 , H05K1/0263 , H05K1/0265 , H05K1/0281 , H05K1/111 , H05K1/117 , H05K3/0097 , H05K3/108 , H05K3/243 , H05K3/361 , H05K2201/056 , H05K2201/09063 , H05K2201/09736 , H05K2201/09781 , H05K2201/10128 , H05K2201/10674 , H05K2201/10681 , H05K2201/2009 , H05K2203/0574 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/05599
摘要： In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.
摘要翻译：在薄膜基材（1）和形成在薄膜基材（1）上的导体布线（23）的薄膜基板（FB）中，导体布线（23）布置成使外部的导体布线厚度连接另一面板或基板的薄膜基板上的连接部分比其他位置的导体布线部分（弯曲部分）（25）的导体布线厚度厚。

116. 发明申请

US20040134685A1 Two signal one power plane circuit board 失效
标题翻译：两个信号一个电源平面电路板
公开(公告)号：US20040134685A1
公开(公告)日：2004-07-15
申请号：US10744142
申请日：2003-12-22
申请人： International Business Machines Corporation
发明人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
IPC分类号： G03G009/00 , H05K001/11 , H01R012/04
CPC分类号： H05K3/445 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2924/0002 , H05K1/056 , H05K1/113 , H05K3/0023 , H05K3/0052 , H05K3/0094 , H05K3/06 , H05K3/108 , H05K3/426 , H05K3/429 , H05K3/44 , H05K3/4623 , H05K3/4641 , H05K2201/0919 , H05K2201/09536 , H05K2201/09554 , H05K2201/096 , H05K2201/10734 , H05K2203/0323 , H05K2203/0574 , H05K2203/0733 , H05K2203/1394 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
摘要翻译：提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路板的方法。光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。边界可以在板的周围，包括从一个电介质层的边缘终止的金属层。提供带有间隙孔的铜箔。第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。开发了通孔，在两个电介质层中对其进行图案化。可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

117. 发明申请

US20030058629A1 Wiring substrate for small electronic component and manufacturing method 审中-公开
标题翻译：小型电子元件接线基板及其制造方法
公开(公告)号：US20030058629A1
公开(公告)日：2003-03-27
申请号：US10253295
申请日：2002-09-24
发明人： Taro Hirai , Gorou Ikegami
IPC分类号： H05K007/10 , H05K007/12
CPC分类号： H01L24/97 , H01L23/49822 , H01L23/49838 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05599 , H01L2224/0603 , H01L2224/32225 , H01L2224/32237 , H01L2224/45099 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/15153 , H01L2924/181 , H01L2924/19043 , H05K1/113 , H05K1/116 , H05K3/064 , H05K3/184 , H05K3/423 , H05K2201/0394 , H05K2201/09563 , H05K2201/09736 , H05K2201/09745 , H05K2203/0369 , H05K2203/0574 , Y10T29/49155 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A wiring substrate for used in a small electronic component. The wiring substrate comprises: an insulating substrate; and a conductive land portion which is formed on a first surface of the insulating substrate and on which an electronic element is to be mounted via conductive adhesive to electrically couple an electrode of the electronic element with the conductive land portion. The thickness of the peripheral portion of the conductive land portion which surrounds the electronic element is thicker than that of the central portion of the conductive land portion. The insulating substrate may also have a conductive land portion which is formed on a second surface of the insulating substrate and which is electrically coupled with the conductive land portion formed on the first surface of the insulating substrate via a through hole penetrating through the insulating substrate.
摘要翻译：一种用于小型电子部件的布线基板。布线基板包括：绝缘基板; 以及形成在所述绝缘基板的第一表面上并且通过导电粘合剂安装电子元件以将所述电子元件的电极与所述导电接地部分电耦合的导电接地部分。围绕电子元件的导电接地部分的周边部分的厚度比导电接地部分的中心部分的厚度厚。绝缘基板还可以具有形成在绝缘基板的第二表面上的导电接合部，并且通过穿过绝缘基板的通孔与形成在绝缘基板的第一表面上的导电接合部电耦合。

118. 发明授权

US06518163B2 Method for forming bumps, semiconductor device, and solder paste 有权
标题翻译：用于形成凸块，半导体器件和焊膏的方法
公开(公告)号：US06518163B2
公开(公告)日：2003-02-11
申请号：US09746336
申请日：2000-12-26
申请人： Seiki Sakuyama , Yasuo Yamagishi , Masataka Mizukoshi
发明人： Seiki Sakuyama , Yasuo Yamagishi , Masataka Mizukoshi
IPC分类号： H01L2144
CPC分类号： H05K3/3484 , H01L21/4853 , H01L21/6835 , H01L23/49883 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1147 , H01L2224/13099 , H01L2224/141 , H01L2224/16145 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01056 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1532 , H05K3/3436 , H05K3/3452 , H05K2201/0266 , H05K2201/10477 , H05K2201/10674 , H05K2201/10734 , H05K2203/043 , H05K2203/0568 , H05K2203/0574 , H05K2203/0577 , H05K2203/0769
摘要： The present invention relates to a bump formation method, comprising the steps of providing a mask, in which a plurality of openings have been formed corresponding to a plurality of electrode pads, to a substrate provided with this plurality of electrode pads, filling the openings with a solder paste, and heat treating the solder paste. The solder paste contains a solder powder. This solder powder is one that contains no more than 10 wt % particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, this solder powder is one that contains no more than 10 wt % particles whose diameter is greater than 40% of the diameter of the openings, or one that contains no more than 30 wt % particles whose diameter is 40 to 100% the thickness of the mask.
摘要翻译：凸点形成方法技术领域本发明涉及一种凸块形成方法，包括以下步骤：将具有多个电极焊盘的多个开口形成的掩模提供给设置有该多个电极焊盘的基板，焊膏，并对焊膏进行热处理。焊膏含有焊料粉末。该焊料粉末是含有不超过10重量％的直径大于掩模厚度且不大于该厚度的1.5倍的颗粒。优选地，该焊料粉末是含有不超过10重量％的直径大于开口直径的40％的颗粒，或者包含不超过30重量％的直径为40至100重量％的颗粒的焊料粉末的面具。

119. 发明申请

US20030014863A1 Method for manufacturing a printed circuit board 失效
标题翻译：印刷电路板的制造方法
公开(公告)号：US20030014863A1
公开(公告)日：2003-01-23
申请号：US10174956
申请日：2002-06-20
申请人： LG Electronics Inc.
发明人： Sung Gue Lee , Yong Il Kim , Yong Soon Jang
IPC分类号： H05K003/02 , H05K003/34
CPC分类号： H01L21/4867 , H05K3/064 , H05K3/243 , H05K2203/0574 , H05K2203/0585 , Y10T29/49117 , Y10T29/49126 , Y10T29/49142 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A printed circuit board (PCB) and method of forming same is performed without incoming lines for plating. The plating is preferably performed on ball pad areas and/or bonding pad areas being the top layer of a multi-layer PCB. A metal layer that later forms circuit patterns serves to supply a power for plating ball pads for solder-ball bonding and bonding pads for wire-bonding with gold (Au). Thus, the gold (Au)-plating is performed prior to forming the circuit patterns. A positive-type first photoresist is coated on the metal layer to form the ball pads and the bonding pads. The coated first photoresist is also used to form circuit patterns. The gold (Au)-plated metal layer of ball pad areas and the bonding pad areas are protected by a second photoresist, which is reactive with a larger quantity of light than the first photoresist. Both first and second photoresists can be concurrently developed.
摘要翻译：执行印刷电路板（PCB）及其形成方法而没有用于电镀的输入线。电镀优选在作为多层PCB的顶层的球垫区域和/或接合焊盘区域上进行。稍后形成电路图案的金属层用于提供用于焊接用于焊球接合的球垫的电力和用于与金（Au）引线接合的接合焊盘。因此，在形成电路图案之前执行镀金（Au）。正极型第一光致抗蚀剂涂覆在金属层上以形成球垫和接合垫。涂覆的第一光致抗蚀剂也用于形成电路图案。金（Au）镀金属层的焊盘区域和焊盘区域被第二光致抗蚀剂保护，第二光致抗蚀剂与第一光致抗蚀剂相比反应性更大。第一和第二光刻胶都可以同时开发。

120. 发明申请

US20020157861A1 Printed circuit board with mixed metallurgy pads and method of fabrication 有权
标题翻译：印刷电路板与混合冶金垫和制造方法
公开(公告)号：US20020157861A1
公开(公告)日：2002-10-31
申请号：US09844814
申请日：2001-04-27
申请人： International Business Machines Corporation
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K001/03
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
摘要翻译：公开了一种制造印刷电路器件的方法，该印刷电路器件包括电绝缘衬底以及形成在衬底顶表面上的第一组，第二组和第三组导体。该方法包括在第二导体组上形成氧化物层; 在氧化物层上形成焊料掩模; 在第一组导体上形成复合层; 以及在所述第三组导体的至少一部分上形成焊料层。

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