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1. 发明申请

US20040172820A1 Multi-Milling Method for the Production of Printed Circuits and the Printed Circuits Thus Obtained 审中-公开
标题翻译：制造印刷电路和印刷电路的多种铣削方法
公开(公告)号：US20040172820A1
公开(公告)日：2004-09-09
申请号：US10707927
申请日：2004-01-26
申请人： LEAR CORPORATION
发明人： Ramon Pinana Lopez
IPC分类号： H05K003/00 , H05K003/02
CPC分类号： H05K1/028 , H05K3/0044 , H05K2201/09036 , H05K2201/09063 , H05K2203/0143 , H05K2203/0228 , Y10T29/49124 , Y10T29/49128 , Y10T29/49156
摘要： A multiple-milling process for manufacturing printed circuits and the printed circuit thus obtained, constituted by a process for preparing the substrate of the printed circuit boards (1) for the production of bending areas (2) from whence to bend said printed circuits (1). This process consists of a multiple-milling system, by means of a mill (3) with special features, comprising a roll provided with multiple polishing strips on its surface, capable of making an undercutting in parallel strips (4) in said bending areas (2) of a printed circuit (1), allowing for their subsequent bending without deteriorating the metallic material conductive tracks adhered to the printed board's substrate on the side opposite the milled surface.
摘要翻译：一种用于制造印刷电路和由此获得的印刷电路的多次铣削工艺，由用于制造用于生产弯曲区域（2）的印刷电路板（1）的基板的方法构成，从而从所述印刷电路（1）弯曲所述印刷电路）。该方法由具有特殊特征的研磨机（3）的多铣削系统组成，包括在其表面上设置有多个抛光条的辊，能够在所述弯曲区域（4）中形成底切（4） 2），允许它们随后的弯曲，而不会使与磨合表面相对的一侧粘附到印刷电路板的基板上的金属材料导电迹线劣化。

2. 发明申请

US20040172819A1 Wiring board, method of manufacturing the same, semiconductor device, electronic module, and electronic apparatus 失效
标题翻译：接线板，其制造方法，半导体器件，电子模块和电子设备
公开(公告)号：US20040172819A1
公开(公告)日：2004-09-09
申请号：US10758698
申请日：2004-01-15
发明人： Fumiaki Karasawa
IPC分类号： H05K003/02 , H05K003/10
CPC分类号： H05K3/3452 , H01L21/486 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16237 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H05K1/111 , H05K3/243 , H05K2201/09381 , H05K2201/0989 , H05K2201/099 , H05K2201/10674 , Y10T29/49155 , H01L2224/05599
摘要： A method of manufacturing a wiring board is provided. The method includes performing a plating process to a land, in a condition that a resist film having an opening for exposing at least the center of the land is formed on a substrate with wires having the land formed thereon, so that a fist portion of an edge of the opening is disposed on the substrate and a second portion of the edge is disposed on the land.
摘要翻译：提供一种制造布线板的方法。该方法包括：在具有在其上形成有焊盘的导线的基板上形成至少具有用于露出焊盘的中心的开口的抗蚀剂膜的情况下，对焊盘进行电镀处理，使得第一部分开口的边缘设置在基板上，边缘的第二部分设置在平台上。

3. 发明申请

US20040163233A1 Methods of forming electrical connections within ferroelectric devices 审中-公开
标题翻译：在铁电设备内形成电气连接的方法
公开(公告)号：US20040163233A1
公开(公告)日：2004-08-26
申请号：US10377156
申请日：2003-02-26
发明人： Stefan Gernhardt , Osamu Hidaka , Jenny Lian , Rainer Bruchhaus , Andreas Hilliger , Nicolas Nagel
IPC分类号： H01F007/06 , H05K003/02
CPC分类号： H01L21/7687 , H01L21/76802 , H01L23/26 , H01L28/55 , H01L28/75 , H01L2924/0002 , Y10T29/4902 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
摘要： A fabrication process for ferroelectric capacitors includes forming openings 23, 30, in the device, into which electrically conductive material 28, 37 can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer 24, 34 of getter material which absorbs contaminants 25, 31, 33 formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers 7 of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.
摘要翻译：用于铁电电容器的制造方法包括在器件中形成开口23,30，导电材料28,37可以插入该开口23,30中，以在器件内形成电连接。每个开口的表面涂覆有吸收材料的层24,34，其吸收在打开过程中形成的污染物25,31,33。这意味着在随后的处理步骤中，污染物不会流向设备的铁电层7，否则可能会导致损坏，例如在随后的结晶阶段。

4. 发明申请

US20040154165A1 Method for manufacturing a probe pin and a probe card 审中-公开
标题翻译：探针和探针卡的制造方法
公开(公告)号：US20040154165A1
公开(公告)日：2004-08-12
申请号：US10723216
申请日：2003-11-26
发明人： Takehisa Takoshima , Wataru Narazaki , Seiichi Hata , Akira Shimokohbe
IPC分类号： H05K003/02 , H01R043/00
CPC分类号： G01R1/07307 , G01R1/07342 , G01R3/00 , Y10T29/49155 , Y10T29/49174 , Y10T29/49204
摘要： A method for manufacturing a probe card comprises the steps of forming a plurality of amorphous alloy layers of a predetermined shape at a predetermined substrate, wherein the amorphous alloy layer has a supercooled liquid temperature area, heating the amorphous alloy layer at the supercooled liquid temperature area, cooling the amorphous alloy layer at a temperature lower than the supercooled liquid temperature area and removing at least a part of the substrate in a state where the amorphous alloy layer is cooled at a temperature lower than the supercooled liquid temperature area.
摘要翻译：一种探针卡的制造方法，其特征在于，在规定的基板上形成规定形状的多个非晶合金层，其特征在于，所述非晶质合金层具有过冷液温区域，在过冷液温区域在低于过冷液体温度区域的温度下冷却非晶合金层，并且在非晶合金层在比过冷液体温度区域低的温度下冷却的状态下除去至少一部分基板。

5. 发明申请

US20040124468A1 Process for forming portions of a compound material inside a cavity and an electronic circuit manufactured therefrom 有权
标题翻译：在腔内形成复合材料的部分的工艺和由其制造的电子电路
公开(公告)号：US20040124468A1
公开(公告)日：2004-07-01
申请号：US10657514
申请日：2003-09-08
发明人： Philippe Coronel , Christophe Regnier , Francois Wacquant , Thomas Skotnicki
IPC分类号： H01L027/01 , H05K003/02
CPC分类号： H01L29/6675 , Y10T29/49155 , Y10T29/49156 , Y10T29/4916 , Y10T29/49165 , Y10T29/49167
摘要： A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.
摘要翻译：在电子电路内形成复合材料部分的工艺包括形成具有面向入口表面的至少一个开口的空腔。该腔还具有内壁，其具有由初始材料（例如硅）制成的至少一个区域。金属沉积在初始材料区域附近。然后将电路加热以在腔内的初始材料区域中形成复合材料（例如，硅化物）的一部分。复合材料由初始材料的元素和沉积的一些金属形成。然后从空腔中除去未形成一些复合材料的多余金属。

6. 发明申请

US20040090500A1 Piezoelectric thin film element, manufacturing method thereof, and liquid ejecting head and liquid ejecting apparatus employing same 有权
标题翻译：压电薄膜元件及其制造方法，以及使用其的液体喷射头和液体喷射装置
公开(公告)号：US20040090500A1
公开(公告)日：2004-05-13
申请号：US10701432
申请日：2003-11-06
申请人： Seiko Epson Corporation
发明人： Masami Murai
IPC分类号： H04R017/00 , H01L041/04 , H05K003/02
CPC分类号： B41J2/14233 , B41J2/161 , B41J2/1623 , B41J2/1628 , B41J2/1642 , B41J2/1645 , B41J2/1646 , B41J2002/14258 , B41J2002/14491 , B41J2202/03 , H01L41/0973 , H01L41/1876 , H01L41/29 , H01L41/318 , Y10T29/42 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49156
摘要： The present invention provides a piezoelectric thin film element with superior piezoelectric properties in which the condition of the crystal of the piezoelectric thin film is appropriately controlled, and a manufacturing method thereof, as well as a inkjet recording head, inkjet printer, or other liquid ejecting apparatus employing the same. The piezoelectric thin film element 40 comprises a top electrode 44, a bottom electrode 42, and a piezoelectric thin film 43 formed between the top electrode 44 and the bottom electrode 42, wherein the piezoelectric thin film 43 is structured so as to comprise a first layer 431 located nearest to the bottom electrode and second layers (433-436) that are located nearer to the top electrode than the first layer and that each have a thickness greater than that of the first layer 431.
摘要翻译：本发明提供一种压电薄膜元件，其压电薄膜元件具有优良的压电薄膜元件，其压电薄膜晶体的状态被适当地控制，其制造方法以及喷墨记录头，喷墨打印机或其它液体喷射使用该装置的装置。压电薄膜元件40包括顶电极44，底电极42和形成在顶电极44和底电极42之间的压电薄膜43，其中压电薄膜43被构造成包括第一层 431位于最靠近底部电极和第二层（433-436），其位于比第一层更靠近顶部电极并且每个具有比第一层431的厚度更大的厚度。

7. 发明申请

US20040078970A1 Method of manufacturing flexible wiring board 有权
标题翻译：柔性电路板制造方法
公开(公告)号：US20040078970A1
公开(公告)日：2004-04-29
申请号：US10646623
申请日：2003-08-22
发明人： Keiichi Naitoh , Toshihiro Shinohara , Masahiro Watanabe
IPC分类号： H05K003/02 , H01K003/10 , C25D005/02
CPC分类号： H05K3/423 , H05K1/0393 , H05K3/0017 , H05K3/06 , H05K3/061 , H05K3/421 , H05K3/4652 , H05K2201/0355 , H05K2201/0394 , H05K2201/09563 , H05K2201/096 , H05K2203/0353 , H05K2203/0554 , H05K2203/0733 , H05K2203/1461 , H05K2203/1476 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
摘要翻译：在本发明中，在第一基膜的表面和背面上分别设置参考导电层和第一表面导电层。第一基膜包括贯穿第一表面导电层的第一通孔。在第一基底膜的表面上依次生长第一化学镀层和第一导电材料之后，将由第一化学镀层，第一导电材料和第一表面导电层构成的第一涂层导电层蚀刻到具有减小的厚度。然后，将第一涂层导电层图案化以形成第一布线层。以这种方式，即使在通过诸如湿蚀刻的各向同性蚀刻对第一涂层导电层进行图案化的情况下，也可以获得期望的图案宽度。

8. 发明申请

US20040055128A1 Manufacturing method of ceramic device using mixture with photosensitive resin 失效
标题翻译：陶瓷器件与感光树脂混合使用的制造方法
公开(公告)号：US20040055128A1
公开(公告)日：2004-03-25
申请号：US10688281
申请日：2003-10-17
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD
发明人： Sang Kyeong Yun , Dong Hoon Kim , Sung June Park
IPC分类号： H05K003/02 , H04R017/00
CPC分类号： H01L41/33 , H01L41/1876 , H04R17/00 , Y10S29/016 , Y10T29/42 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： The present invention relates a manufacturing method of ceramic device either comprising the steps of forming by layer accumulation of a lower electrode, a piezoelectric/electrostrictive layer, and an upper electrode on a substrate using a mixture of photosensitive resin and metal or piezoelectric/electrostrictive ceramic; and patterning by light exposure at a single time, or repeating the step of patterning by light exposure after formation for layer by layer, or a manufacturing method of ceramic device either comprising the steps of forming by layer accumulation of a piezoelectric/electrostrictive layer and an upper electrode on a metal substrate using a mixture of photosensitive resin and metal or piezoelectric/electrostrictive ceramic; and patterning by light exposure at a single time, or repeating the step of patterning by light exposure after formation for layer by layer, thereby ceramic device of high shape ratio can be produced and precision degree is very high so as to produce a ceramic device very precise in arrangement between layers or with infrastructure so that another effect may be made to systematically prevent the short between upper and lower electrodes.
摘要翻译：本发明涉及一种陶瓷器件的制造方法，包括以下步骤：使用感光性树脂和金属或压电/电致伸缩陶瓷的混合物在基板上形成下层电极，压电/电致伸缩层和上电极的层叠积 ; 以及通过单次曝光进行图案化，或者重复通过逐层形成后的曝光进行图案化的步骤，或陶瓷器件的制造方法，包括以下步骤：形成压电/电致伸缩层的层叠积和使用感光性树脂和金属或压电/电致伸缩陶瓷的混合物在金属基板上形成上部电极; 并且通过单次曝光进行图案化，或者在形成后重复通过曝光进行图案化的步骤，从而可以产生高形状比的陶瓷器件，并且精度非常高，以便非常地制造陶瓷器件精确地布置在层之间或与基础设施之间，使得可以进行另一个效果来系统地防止上部和下部电极之间的短路。

9. 发明申请

US20040055126A1 Fabrication of liquid emission device with symmetrical electrostatic mandrel 失效
标题翻译：具有对称静电心轴的液体排放装置的制造
公开(公告)号：US20040055126A1
公开(公告)日：2004-03-25
申请号：US10254350
申请日：2002-09-25
申请人： Eastman Kodak Company
发明人： Michael J. DeBar , Gilbert A. Hawkins , James M. Chwalek
IPC分类号： H05K003/02 , B23P017/00 , H04R017/00
CPC分类号： B41J2/16 , B41J2/14314 , B41J2/1623 , B41J2/1626 , B41J2/1631 , B41J2/1632 , B41J2/1639 , B41J2/1642 , Y10S29/037 , Y10T29/42 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49401
摘要： A liquid emission device includes a chamber having a nozzle orifice. Separately addressable dual electrodes are positioned on opposite sides of a central electrode. The three electrodes are aligned with the nozzle orifice. A rigid electrically insulating coupler connects the two addressable electrodes. To eject a drop, an electrostatic charge is applied to the addressable electrode nearest to the nozzle orifice, which pulls that electrode away from the orifice, drawing liquid into the expanding chamber. The other addressable electrode moves in conjunction, storing potential energy in the system. Subsequently the addressable electrode nearest to the nozzle is de-energized and the other addressable electrode is energized, causing the other electrode to be pulled toward the central electrode in conjunction with the release of the stored elastic potential energy. This action pressurizes the liquid in the chamber behind the nozzle orifice, causing a drop to be ejected from the nozzle orifice.
摘要翻译：液体排放装置包括具有喷嘴孔的室。单独寻址的双电极位于中心电极的相对侧上。三个电极与喷嘴孔对齐。刚性电绝缘耦合器连接两个可寻址电极。为了喷射液滴，静电电荷施加到最接近喷嘴孔的可寻址电极，该电极将该电极拉离孔口，将液体引入扩张室。其他可寻址电极一起移动，将势能存储在系统中。随后，最接近喷嘴的可寻址电极被断电，另一个可寻址电极通电，使另一个电极与存储的弹性势能的释放一起被拉向中心电极。这种作用使喷嘴孔后面的腔中的液体加压，导致从喷嘴口喷出的液滴。

10. 发明申请

US20030182797A1 Fabrication method of circuit board 失效
标题翻译：电路板制作方法
公开(公告)号：US20030182797A1
公开(公告)日：2003-10-02
申请号：US10176122
申请日：2002-06-20
申请人： UltraTera Corporation
发明人： Chung-Che Tsai , Jin-Chuan Bai
IPC分类号： H05K003/02 , H05K003/00
CPC分类号： H05K3/28 , H05K2201/0959 , H05K2203/0582 , Y10T29/49124 , Y10T29/49128 , Y10T29/49144 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T29/49171
摘要： A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed to outside of the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.
摘要翻译：提出了一种电路板的制造方法，其中芯层形成有多个导电迹线，并且将光致抗蚀剂分别施加在导电迹线的端子上。然后，在芯层上施加不可焊接的材料以覆盖导电迹线，绝缘材料除外，并且不可焊接材料适于与绝缘材料表面齐平，从而使绝缘材料暴露到不可焊材料的外面。最后，从芯层去除绝缘材料以露出导电迹线的端子，其中暴露的端子用作可焊接焊球，焊料凸块或接合线的接合焊盘或接合指状物。该电路板通过简化的工艺成本有效地制造，并且有益于精确地暴露接合焊盘或接合指，从而显着提高制造的电路板的产量。

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