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111. 发明申请

US20030119467A1 Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications 有权
公开(公告)号：US20030119467A1
公开(公告)日：2003-06-26
申请号：US10358563
申请日：2003-02-05
申请人： Silicon Laboratories, Inc.
发明人： David R. Welland , Caiyi Wang
IPC分类号： H04B001/06
CPC分类号： H03L7/193 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/199 , H03L7/23 , H03L2207/06
摘要： A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

112. 发明申请

US20030117188A1 Semiconductor device having internal circuit operating in synchronization with internal clock signal 失效
标题翻译：具有与内部时钟信号同步工作的内部电路的半导体器件
公开(公告)号：US20030117188A1
公开(公告)日：2003-06-26
申请号：US10212707
申请日：2002-08-07
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Jingo Nakanishi
IPC分类号： H03L007/00
CPC分类号： H03L7/0805 , G06F1/08 , H03L7/0814 , H03L7/089 , H03L7/0997 , H03L7/23
摘要： A semiconductor integrated circuit chip includes a replica circuit for delaying a reference clock signal, a delay detector for controlling a delay time of the replica circuit such that the delay time of replica circuit becomes one-fourth the period of the reference clock signal, and an EX-OR gate that receives the reference clock signal and an output clock signal from replica circuit for supplying to a logic circuit an internal clock signal that is obtained by multiplying the reference clock signal by two. Thus, the consumed power can be kept small in comparison with the conventional example in which an internal clock signal is propagated on a clock line.
摘要翻译：半导体集成电路芯片包括用于延迟参考时钟信号的复制电路，用于控制复制电路的延迟时间的延迟检测器，使得复制电路的延迟时间变为参考时钟信号的周期的四分之一，接收参考时钟信号的EX-OR门和来自复制电路的输出时钟信号，以向逻辑电路提供通过将参考时钟信号乘以2而获得的内部时钟信号。因此，与内部时钟信号在时钟线上传播的传统例子相比，消耗功率可以保持较小。

113. 发明申请

US20030030497A1 Integrated VCO having an improved tuning range over process and temperature variations 有权
标题翻译：集成VCO在过程和温度变化方面具有改进的调谐范围
公开(公告)号：US20030030497A1
公开(公告)日：2003-02-13
申请号：US10171762
申请日：2002-06-17
申请人： Broadcom Corporation
发明人： Ralph Duncan , Tom W. Kwan
IPC分类号： H03L007/00
CPC分类号： H03L7/23 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/08 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H03B5/1209 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/364 , H03B2200/0038 , H03B2201/025 , H03B2201/0266 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L1/023 , H03L7/10 , H01L2924/00
摘要： An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.
摘要翻译：具有改进的调谐范围超过过程和温度变化的集成VCO。因此，在本发明的本实施例中提供了集成VCO。 VCO包括：衬底，响应于设置在衬底上的VCO状态变量的VCO调谐控制电路，以及设置在衬底上的VCO，具有落在VCO调谐范围内的调谐控制电压输入，用于调节VCO频率输出，并且其调谐范围由调谐控制电路响应于VCO状态变量而调整。

114. 发明授权

US06483390B2 Method and apparatus for synthesizing dual band high-frequency signals for wireless communications 有权
公开(公告)号：US06483390B2
公开(公告)日：2002-11-19
申请号：US09935527
申请日：2001-08-23
申请人： David R. Welland
发明人： David R. Welland
IPC分类号： H03L700
CPC分类号： H03L7/23 , H03J2200/10 , H03L7/07 , H03L7/099 , H03L7/113 , H03L7/18 , H03L7/199
摘要： A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.

115. 发明申请

US20020145475A1 Dual conversion RF synthesizer utilizing improved push-push VCO design 审中-公开
标题翻译：双转换RF合成器利用改进的推挽VCO设计
公开(公告)号：US20020145475A1
公开(公告)日：2002-10-10
申请号：US09829609
申请日：2001-04-10
申请人： APA Wireless Technologies
发明人： Eliot Fenton , Claudio Cassina , Zhong Han , Joseph Paniccia
IPC分类号： H03B005/18 , H03L007/18 , H03L007/197
CPC分类号： H03L7/23 , H03B5/1841 , H03B21/02 , H03L7/091 , H03L7/1974 , H03L7/20 , H03L2207/10 , H03L2207/12
摘要： A dual conversion, noise resistant, digitally-controlled mm-wave frequency synthesizer for generating rapidly-tunable RF signals. The prime signal-generation source is a 3.0-3.2 GHz low noise wide band voltage controlled oscillator (nullvconull). The oscillator includes a buried stripline hairpin resonator having dual-tuning circuits to increase bandwidth coverage and unique bias circuitry to improve phase noise. The oscillator frequency is multiplied by a factor of two, yielding a 6.0-6.4 GHz signal that is mixed with a fixed locally generated carrier of 3900 MHz, the output of which represents the first Intermediate Frequency (IF). This IF is then mixed with 1950 MHz (3900 MHz divided by two), yielding a second IF that covers the 188 to 550 MHz range. The 2nd IF is divided down and phase locked to an external reference using a commercially available chip set. The 6.0-6.4 phase locked signal is then re-mixed with the 3.0-3.2 GHz output form the oscillator, thereby yielding a 9.0-9.6 GHz signal. The 9.0-9.6 signal is then multiplied by two to yield a 18.0-19.2 GHz signal. This signal is amplified by a mm-wave amplifier, which also contains a detector diode for output power monitoring. The voltage from the detector diode is fed back to an on-board microcontroller which maintains the RF output power within an acceptable range. By using harmonically related signals for the mix approach, no mixer spurious signals are generated.
摘要翻译：双转换，抗噪声，数字控制的mm波频率合成器，用于产生快速可调RF信号。主要信号源是3.0-3.2 GHz低噪声宽带压控振荡器（“vco”）。所述振荡器包括具有双调谐电路以增加带宽覆盖率和唯一偏置电路以改善相位噪声的掩埋带状线发夹谐振器。振荡器频率乘以因子2，产生与3900MHz的固定本地生成的载波混合的6.0-6.4GHz信号，其输出表示第一中间频率（IF）。然后将该IF与1950MHz（3900MHz除以2）混合，产生覆盖188至550MHz范围的第二IF。使用市售芯片组将第二个IF分频并锁定到外部参考。然后将6.0-6.4锁相信号与振荡器的3.0-3.2 GHz输出重新混合，从而产生9.0-9.6 GHz信号。然后将9.0-9.6信号乘以2，以产生18.0-19.2 GHz信号。该信号由毫米波放大器放大，该放大器还包含用于输出功率监测的检测器二极管。来自检测器二极管的电压被反馈到板上微控制器，其将RF输出功率维持在可接受的范围内。通过使用混合方式的谐波相关信号，不产生混频器杂散信号。

116. 发明授权

US06463013B1 Clock generating apparatus and method thereof 有权
标题翻译：时钟发生装置及其方法
公开(公告)号：US06463013B1
公开(公告)日：2002-10-08
申请号：US09631293
申请日：2000-08-02
申请人： Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
发明人： Kuo-Ping Liu , Jiin Lai , Jyh-fong Lin , Yu-Wei Lin
IPC分类号： G04F500
CPC分类号： H03L7/199 , G06F1/06 , H03L7/07 , H03L7/23
摘要： A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.
摘要翻译：一种用于产生不同频率的时钟信号的时钟产生装置和方法。时钟发生装置和方法接收和分割主时钟信号以获得参考时钟信号。然后，参考时钟信号和第一反馈时钟信号被锁相以获得第一时钟信号。此外，参考时钟信号和第二反馈时钟信号被锁相以获得第二时钟信号。复位信号和第一时钟信号由分频器接收。然后分频器输出第一反馈时钟信号。另一分频器接收复位信号和第二时钟信号，然后输出第二反馈时钟信号。

117. 发明授权

US06445039B1 System and method for ESD Protection 有权
标题翻译： ESD保护的系统和方法
公开(公告)号：US06445039B1
公开(公告)日：2002-09-03
申请号：US09483551
申请日：2000-01-14
申请人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
发明人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
IPC分类号： H01L2972
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。还提供每个引脚上的分流器，以放电ESD积聚。分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

118. 发明申请

US20020118069A1 Reference clock generation system and device 有权
标题翻译：参考时钟生成系统和设备
公开(公告)号：US20020118069A1
公开(公告)日：2002-08-29
申请号：US10078232
申请日：2002-02-15
申请人： ROHM CO., LTD.
发明人： Masayu Fujiwara , Yasunori Kawamura
IPC分类号： H03L007/00
CPC分类号： H03L7/23 , Y10S331/02
摘要： A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock. The frequency division ratios are distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.
摘要翻译：一种时钟发生系统，具有多个PLL电路级串联连接，使得分频比分布在所述各个PLL电路级上以达到所述预定比率，第一PLL电路级接收所述第一时钟和最后一个PLL电路级输出第二时钟分频比分布成使得至少在除第一级以外的PLL电路级中，各个PLL电路级的S / N比小于与时钟生成相关联的本底噪声的S / N比系统。

119. 发明授权

US06405024B1 Frequency synthesizer with a phase-locked loop for receiving and processing signals in different frequency bands 有权
标题翻译：具有锁相环的频率合成器，用于接收和处理不同频带的信号
公开(公告)号：US06405024B1
公开(公告)日：2002-06-11
申请号：US09182278
申请日：1998-10-29
申请人： Edmund Goetz , Shen Feng , Markus Scholz , Georg Lipperer , Stefan Beyer
发明人： Edmund Goetz , Shen Feng , Markus Scholz , Georg Lipperer , Stefan Beyer
IPC分类号： H04B106
CPC分类号： H03L7/23 , H04B1/403
摘要： A frequency synthesizer for a radio terminal with which a dual-band and/or dual-mode switchover is possible in a simple manner. The frequency synthesizer has a double phase-locked loop with a high-frequency portion and an intermediate-frequency portion, each with one divider and one counter in a feedback branch. There is at least one memory for holding a plurality of divider values for the counter in the intermediate-frequency portion. The counter in the high-frequency portion is coupled to the memory in such a way that when a new divider value is written into the counter of the high-frequency portion, an associated divider value from the memory is written into the counter of the intermediate-frequency portion. In this way, the frequency generated by the intermediate-frequency divider is adapted to the frequency generated in the high-frequency portion in such a way that the requisite operating frequencies of each active mobile radio system are set automatically. In the same way, the dual-mode switchover can be carried out by coupling a further memory with further divider values for the counter of the high-frequency portion.
摘要翻译：一种用于无线终端的频率合成器，可以以简单的方式进行双频和/或双模切换。频率合成器具有双重锁相环，其具有高频部分和中频部分，每个在反馈分支中具有一个分频器和一个计数器。存在至少一个存储器，用于在中频部分中保存用于计数器的多个除法器值。高频部分中的计数器以这样的方式耦合到存储器，即当新的分频器值被写入高频部分的计数器时，来自存储器的相关联的分频值被写入中间级的计数器频率部分。以这种方式，中频分频器产生的频率适应于高频部分中产生的频率，使得每个有源移动无线电系统的必要操作频率被自动设置。以同样的方式，可以通过将另外的存储器与用于高频部分的计数器的另外的分频器值进行耦合来执行双模切换。

120. 发明申请

US20020037702A1 Transmitting and receiving apparatus 失效
标题翻译：发射和接收设备
公开(公告)号：US20020037702A1
公开(公告)日：2002-03-28
申请号：US09968773
申请日：2001-10-03
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Hiroaki Nagano , Kazuhiro Mori , Kenji Itoh
IPC分类号： H04B001/40
CPC分类号： H03D7/163 , H03L7/23 , H04B1/00 , H04B1/403 , H04B1/406
摘要： A reception carrier wave, of which a frequency fL0 agrees with a frequency fRX of a reception wave, is generated, a first transmission carrier wave, of which a frequency fL1 is equivalent to twice of a difference value between the reception frequency and a frequency fTX of a transmission wave, is generated, and a second transmission carrier wave of which a frequency fL2 is equivalent to a difference value between the frequency fL0 and the frequency fL1, is generated. The reception carrier wave mixed with the reception wave to produce a reception signal. The frequency of the first transmission carrier wave is halved, and the first transmission carrier wave is mixed with a transmission signal to produce a modulated wave. The second transmission carrier wave is mixed with the modulated wave to produce a transmission wave. Therefore, because either the frequency of the first transmission carrier wave or the frequency of the second transmission carrier wave does not agree with each of the frequency of the modulated wave and the frequency fTX, the degradation of the modulation precision on a transmission side can be prevented. Also, because the frequency of the first transmission carrier wave is halved, the interference of the first transmission carrier wave with the transmission signal band can be reduced.
摘要翻译：产生频率fL0与接收波的频率fRX一致的接收载波，其频率fL1等于接收频率和频率fTX之间的差值的两倍的第一传输载波并且产生频率fL2等于频率fL0和频率fL1之间的差值的第二传输载波。接收载波与接收波混合以产生接收信号。第一传输载波的频率减半，并且第一传输载波与传输信号混合以产生调制波。第二传输载波与调制波混合以产生传输波。因此，由于第一发送载波的频率或第二发送载波的频率与调制波的频率和频率fTX不一致，所以发送侧的调制精度的劣化可以是防止了此外，由于第一传输载波的频率减半，所以可以减少第一传输载波与传输信号频带的干扰。

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