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1. 发明申请

US20040233009A1 Method and apparatus for driving a direct current or voltage controlled oscillator with modulation slope feedback 有权
标题翻译：用调制斜率反馈驱动直流或压控振荡器的方法和装置
公开(公告)号：US20040233009A1
公开(公告)日：2004-11-25
申请号：US10833418
申请日：2004-04-27
申请人： ATMEL Germany GmbH
发明人： Juergen Eckert , Thorsten Fahlbusch , Burkhard Gehring , Hans-Werner Groh , Horst Haefner , Hermann Hammel , Michael Hecker , Gerald Krimmer , Reinhard Reimann , Wolfgang Roeper , Friedemann Schmidt , Juergen Schnabel , Wolfgang Schneider , Michael Vogt , Hans-Peter Waible
IPC分类号： H03B005/18
CPC分类号： H03C3/0958 , H03C3/095
摘要： A d.c. signal controlled oscillator includes a frequency-determining network having a control input and a modulation input. A phase regulating loop includes the oscillator and components that provide a control signal to the control input. A circuit apparatus for driving the oscillator includes a modulation generator that provides a modulation signal to the modulation input, and a circuit arrangement that autonomously generates a signal depending on and representing a slope of the modulation and provides this slope signal to the modulation generator, which generates the modulation signal dependent on the slope signal. A method of operating the oscillator involves switching a frequency divider successively to two different frequencies, respectively sampling and holding the two different arising control voltages, forming a difference between the two control voltages, and activating the modulation generator so that a modulation swing of the modulation signal is determined by this difference between the control voltages.
摘要翻译：一个d.c. 信号控制振荡器包括具有控制输入和调制输入的频率确定网络。相位调节回路包括振荡器和向控制输入提供控制信号的组件。用于驱动振荡器的电路装置包括：向调制输入提供调制信号的调制发生器，以及根据并表示调制斜率自主生成信号的电路装置，并将该斜率信号提供给调制发生器，根据斜率信号产生调制信号。一种操作振荡器的方法包括将分频器连续地切换到两个不同的频率，分别采样和保持两个不同的出现的控制电压，形成两个控制电压之间的差异，并激活调制发生器，使得调制的调制摆幅信号由控制电压之间的差异决定。

2. 发明申请

US20040095197A1 Lock detector circuit for phase locked loop 失效
标题翻译：用于锁相环的锁定检测电路
公开(公告)号：US20040095197A1
公开(公告)日：2004-05-20
申请号：US10299313
申请日：2002-11-18
发明人： David Y. Wang , Jyn-Bang Shyu
IPC分类号： H03B005/18
CPC分类号： H03L7/095 , Y10S331/02
摘要： A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time. This condition causes the logic gate to issue an enabling signal to the divide-by-64 counters. The divide-by-64 counter starts to count to full cycle and then the lock detect signal is high, indicating the PLL is in locked condition.
摘要翻译：一种锁相环的方法和锁定检测电路，用于检测参考信号与反馈信号之间的锁定两个阶段：锁定检测阶段和锁定断言阶段。检测器电路包括耦合到第一，第二D触发器，OR逻辑门和AND门的延迟电路。在锁定检测中，锁定检测器电路将参考输入时钟的相位与反馈时钟进行比较。如果这些时钟的相位在容差范围内不同，则第一和第二D触发器的采样时钟输出是不同的。这种情况导致逻辑门向64分频计数器发出复位信号。因此，锁定检测信号为低，表示PLL未处于锁定状态。在锁定断言阶段，如果两个相位相同或在容差范围内，则第一个和第二个D触发器的采样时钟输出同时相同或都是低电平。这种情况导致逻辑门向64位计数器发出使能信号。 64位计数器开始计数到全周期，然后锁定检测信号为高电平，表示PLL处于锁定状态。

3. 发明申请

US20040012450A1 Broadband voltage controlled oscillator supporting improved phase noise 失效
标题翻译：宽带压控振荡器支持改善相位噪声
公开(公告)号：US20040012450A1
公开(公告)日：2004-01-22
申请号：US10197606
申请日：2002-07-18
发明人： Glao M. Nguyen
IPC分类号： H03B005/18 , H03L007/00
CPC分类号： H03B5/1231 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03J2200/36
摘要： VCO (voltage controlled oscillator) circuits typically exhibit a frequency dependent variation in their output signal with respect to a tuning voltage applied to a tuning port on the VCO circuit. For a fixed tuning voltage the VCO circuit forms a stable oscillator. However, the stable oscillator formed is susceptible to both internal and external noise sources. Forming a VCO circuit from components such as varactors facilitates frequency stability and decreased noise susceptibility of the VCO circuit. A VCO formed from such components advantageously uses a summed capacitance of two or more varactors to provide decreased phase noise. Using a summed capacitance of the varactors reduces changes in output signal frequency with respect to changes in tuning voltage and thereby reduces the effects of noise by reducing a slope of this dependence.
摘要翻译： VCO（压控振荡器）电路相对于施加到VCO电路上的调谐端口的调谐电压通常表现出其输出信号的频率相关变化。对于固定的调谐电压，VCO电路形成稳定的振荡器。然而，形成的稳定振荡器对内部和外部噪声源都是易受影响的。从诸如变容二极管的组件形成VCO电路有助于频率稳定性和降低VCO电路的噪声敏感性。由这些组件形成的VCO有利地使用两个或更多个可变电抗器的总和电容来提供降低的相位噪声。使用可变电抗器的总和电容可以减小输出信号频率相对于调谐电压变化的变化，从而通过减小该依赖性的斜率来减少噪声的影响。

4. 发明申请

US20030210100A1 Oscillator having voltage dividing circuit 失效
标题翻译：具有分压电路的振荡器
公开(公告)号：US20030210100A1
公开(公告)日：2003-11-13
申请号：US10435042
申请日：2003-05-12
申请人： FUJITSU MEDIA DEVICES LIMITED
发明人： Nobuaki Matsuo , Alejandro Puel
IPC分类号： H03B005/18
CPC分类号： H03B5/1847 , H03B2201/0208
摘要： An oscillator includes a resonance circuit, and a feedback circuit coupled to the resonance circuit. The resonance circuit includes a main resonance element circuit, and a voltage dividing circuit that divides an output voltage of the main resonance element circuit and applies a divided voltage to the feedback circuit.
摘要翻译：振荡器包括谐振电路和耦合到谐振电路的反馈电路。谐振电路包括主谐振元件电路和分压电路，其分压主谐振元件电路的输出电压并将分压施加到反馈电路。

5. 发明申请

US20020097100A1 Optimally designed dielectric resonator oscillator (DRO) and method therefor 审中-公开
标题翻译：最优设计的介质谐振器（DRO）及其方法
公开(公告)号：US20020097100A1
公开(公告)日：2002-07-25
申请号：US09771353
申请日：2001-01-25
发明人： Donnie W. Woods , Charles D. Pitcher , Roy Baldarrama
IPC分类号： H03B005/18
CPC分类号： H03D7/163 , H03B5/1876 , H03B2201/0208
摘要： A design methodology for a DRO that facilitates the development of the DRO. The methodology involves providing an electrical length of approximately 180 degrees or a multiple thereof from a region interior to a field effect transistor to a puck-resonator line interaction region, providing an electrical length of approximately 180 degrees or a multiple thereof from a region interior to the field effect transistor to the signal end of a source feedback transmission line, and providing an electrical length of approximately 90 degrees or an odd multiple thereof from a varactor diode signal ground to a puck-tuning line interaction region. Other aspects relate to a DRO resonator transmission line and a DRO tuning transmission line having a portion formed on a higher dielectric substrate to concentrate the electromagnetic field, and a portion on a lower dielectric substrate to expand the electromagnetic field near the dielectric resonator puck.
摘要翻译： DRO的设计方法，有助于DRO的发展。该方法涉及提供大约180度的电长度或其从场效应晶体管内部的区域到圆盘谐振器线相互作用区域的电子长度，从而从区域内部到内部提供大约180度的电长度或其多倍该场效应晶体管连接到源极反馈传输线的信号端，并且从变容二极管信号接地提供大约90度或其奇数倍的电长度到冰球调谐线相互作用区域。其他方面涉及DRO谐振器传输线和DRO调谐传输线，DRO调谐传输线具有形成在较高电介质基底上的部分以集中电磁场，以及在下电介质基底上的一部分以扩展介质谐振器圆盘附近的电磁场。

6. 发明申请

US20020008592A1 Oscillator with constant output level over oscillation frequency range 失效
标题翻译：在振荡频率范围内具有恒定输出电平的振荡器
公开(公告)号：US20020008592A1
公开(公告)日：2002-01-24
申请号：US09902347
申请日：2001-07-10
申请人： Alps Electric Co., Ltd.
发明人： Akiyuki Yoshisato , Kazuhiko Ueda , Hiroaki Kukita
IPC分类号： H03B005/12 , H03B005/18
CPC分类号： H03B5/1847 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B5/1841
摘要： An oscillator includes an oscillation circuit unit and an amplification circuit unit of the common-base type. The oscillation circuit unit includes an oscillation transistor and a resonance circuit, the collector of the oscillation transistor being grounded via a first capacitor. The amplification circuit unit includes an amplification transistor, the emitter thereof being directly connected to the collector of the oscillation transistor and the base thereof being grounded via a second capacitor. The resonance circuit is connected between the base of the oscillation transistor and the ground. An oscillation signal output from the collector of the oscillation transistor is input to the emitter of the amplification transistor while partially being bypassed to the ground via the first capacitor. Negative feedback is provided to the amplification transistor in association with the second capacitor.
摘要翻译：振荡器包括共用基极型振荡电路单元和放大电路单元。振荡电路单元包括振荡晶体管和谐振电路，振荡晶体管的集电极经由第一电容器接地。放大电路单元包括放大晶体管，其发射极直接连接到振荡晶体管的集电极，其基极经由第二电容器接地。谐振电路连接在振荡晶体管的基极与地之间。从振荡晶体管的集电极输出的振荡信号被输入到放大晶体管的发射极，同时部分地经由第一电容器旁路到地。与第二电容器相关联地向放大晶体管提供负反馈。

7. 发明申请

US20030193374A1 PLL for clock recovery with initialization sequence 有权
标题翻译： PLL用于具有初始化序列的时钟恢复
公开(公告)号：US20030193374A1
公开(公告)日：2003-10-16
申请号：US10412448
申请日：2003-04-11
发明人： James J. McDonald II , Ronald B. Hulfachor , Jim Wunderlich
IPC分类号： H03B005/18
CPC分类号： H03L7/0891 , H03L7/095 , H03L7/0995 , H03L7/10 , H03L2207/14 , H04L7/033 , H04L7/044 , H04L7/10
摘要： A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
摘要翻译：使用锁相环电路来提供从串行数据流中进行数据位恢复的定时时钟。该系统锁定到SYNC信号，优选地是具有等于完全成帧的串行数据字的时间的周期的低频百分之五十的占空比方波。当检测到启动信号转换时，系统被阻止试图锁定到数据信号边沿转换。但是，该系统提供适合于在各个数据位中计时的信号。

8. 发明申请

US20020093388A1 Voltage-controlled oscillator and communication device 失效
标题翻译：压控振荡器和通讯装置
公开(公告)号：US20020093388A1
公开(公告)日：2002-07-18
申请号：US09985940
申请日：2001-11-06
发明人： Toshikazu Imaoka , Katsuaki Onoda
IPC分类号： H03B005/18
CPC分类号： H03B5/1852
摘要： An impedance transformer is so designed that the impedance and the reactance of a tuning part reach zero at a central control voltage. An open stub is employed for setting the characteristic impedance of a tuning stub to the minimum value when a variable reactance circuit is inductive while setting the characteristic impedance to null1.22 times the reactance of the variable reactance circuit when the variable reactance circuit is capacitive. A short stub is employed for setting the characteristic impedance of the tuning stub to 0.82 times the reactance of the variable reactance circuit when the variable reactance is inductive, while setting the characteristic impedance to the maximum when the variable reactance circuit is capacitive.
摘要翻译：阻抗变换器被设计成使得调谐部件的阻抗和电抗在中央控制电压下达到零。当可变电抗电路为电感时，将可变电抗电路的特性阻抗设定为可变电抗电路的电抗的-1.22倍，使可变短路的特性阻抗设定为最小值。当可变电抗为电感时，将可变电抗电路的电抗设置为可变电抗电路的电抗的0.82倍，同时在可变电抗电路为电容时将特性阻抗设定为最大值时，采用短截线。

9. 发明申请

US20020033740A1 Dielectric resonance oscillation circuit 失效
标题翻译：介质共振振荡电路
公开(公告)号：US20020033740A1
公开(公告)日：2002-03-21
申请号：US09773600
申请日：2001-02-02
发明人： Hitoshi Nitta
IPC分类号： H03B005/18
CPC分类号： H03B5/187
摘要： In a feedback type oscillation circuit including a first microstrip line connected to a signal input terminal of a transistor, a second microstrip line connected to a signal output terminal of the transistor, and a dielectric resonator coupled with the microstrip lines at high frequency, the first and second microstrip lines are provided with patterns that are branched off from the respective microstrip lines, each at an arbitrary angle.
摘要翻译：在包括连接到晶体管的信号输入端的第一微带线的反馈型振荡电路中，连接到晶体管的信号输出端的第二微带线和与微带线以高频耦合的介质谐振器，第一并且第二微带线设置有从各个微带线分支的图案，每个以任意角度分布。

10. 发明申请

US20010043125A1 Oscillator 审中-公开
标题翻译：振荡器
公开(公告)号：US20010043125A1
公开(公告)日：2001-11-22
申请号：US09731004
申请日：2000-12-06
申请人： Murata Manufacturing Co., Ltd.
发明人： Fumitoshi Sato
IPC分类号： H03B005/12 , H03B005/18
CPC分类号： H03B5/1847
摘要： An oscillator with reduced phase noise. The oscillator includes a resonance circuit and an amplifying circuit. The amplifying circuit has an amplifier. An impedance element having a frequency characteristic is connected to the amplifier and, therefore, the power amplification of the amplifying circuit is decreased by at least 3 dB in a frequency band lower than about 0.5 times an oscillating frequency f0 or higher than about 2f0, as compared to the power amplification of said amplifying circuit at the oscillating frequency f0.
摘要翻译：具有降低相位噪声的振荡器。振荡器包括谐振电路和放大电路。放大电路具有放大器。具有频率特性的阻抗元件连接到放大器，因此放大电路的功率放大在低于振荡频率f0的约0.5倍或高于约2f0的频带中降低至少3dB，如与振荡频率f0处的所述放大电路的功率放大相比。

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